include/configs/P1010RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * P010 RDB board configuration file
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <asm/config_mpc85xx.h>
  14 #define CONFIG_NAND_FSL_IFC
  15
  16 #ifdef CONFIG_SDCARD
  17 #define CONFIG_SPL_FLUSH_IMAGE
  18 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  19 #define CONFIG_SPL_PAD_TO               0x18000
  20 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
  21 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  22 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  23 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  24 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  25 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  26 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  27 #define CONFIG_SPL_MMC_BOOT
  28 #ifdef CONFIG_SPL_BUILD
  29 #define CONFIG_SPL_COMMON_INIT_DDR
  30 #endif
  31 #endif
  32
  33 #ifdef CONFIG_SPIFLASH
  34 #ifdef CONFIG_SECURE_BOOT
  35 #define CONFIG_RAMBOOT_SPIFLASH
  36 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  37 #else
  38 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  39 #define CONFIG_SPL_FLUSH_IMAGE
  40 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  41 #define CONFIG_SPL_PAD_TO                       0x18000
  42 #define CONFIG_SPL_MAX_SIZE                     (96 * 1024)
  43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  47 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  48 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  49 #define CONFIG_SPL_SPI_BOOT
  50 #ifdef CONFIG_SPL_BUILD
  51 #define CONFIG_SPL_COMMON_INIT_DDR
  52 #endif
  53 #endif
  54 #endif
  55
  56 #ifdef CONFIG_NAND
  57 #ifdef CONFIG_SECURE_BOOT
  58 #define CONFIG_SPL_INIT_MINIMAL
  59 #define CONFIG_SPL_NAND_BOOT
  60 #define CONFIG_SPL_FLUSH_IMAGE
  61 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  62
  63 #define CONFIG_SPL_MAX_SIZE             8192
  64 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
  65 #define CONFIG_SPL_RELOC_STACK          0x00100000
  66 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
  67 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  68 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  69 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
  70 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  71 #else
  72 #ifdef CONFIG_TPL_BUILD
  73 #define CONFIG_SPL_NAND_BOOT
  74 #define CONFIG_SPL_FLUSH_IMAGE
  75 #define CONFIG_SPL_NAND_INIT
  76 #define CONFIG_SPL_COMMON_INIT_DDR
  77 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  78 #define CONFIG_TPL_TEXT_BASE            0xD0001000
  79 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  80 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
  81 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  82 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  83 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
  84 #elif defined(CONFIG_SPL_BUILD)
  85 #define CONFIG_SPL_INIT_MINIMAL
  86 #define CONFIG_SPL_NAND_MINIMAL
  87 #define CONFIG_SPL_FLUSH_IMAGE
  88 #define CONFIG_SPL_MAX_SIZE             8192
  89 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  90 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
  91 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
  92 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
  93 #endif
  94 #define CONFIG_SPL_PAD_TO       0x20000
  95 #define CONFIG_TPL_PAD_TO       0x20000
  96 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
  97 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  98 #endif
  99 #endif
 100
 101 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
 102 #define CONFIG_RAMBOOT_NAND
 103 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
 104 #endif
 105
 106 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 107 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 108 #endif
 109
 110 #ifdef CONFIG_TPL_BUILD
 111 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
 112 #elif defined(CONFIG_SPL_BUILD)
 113 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 114 #else
 115 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 116 #endif
 117
 118 /* High Level Configuration Options */
 119 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
 120
 121 #if defined(CONFIG_PCI)
 122 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 123 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
 124 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 125 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 126 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
 127 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 128
 129 /*
 130  * PCI Windows
 131  * Memory space is mapped 1-1, but I/O space must start from 0.
 132  */
 133 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 134 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe Slot"
 135 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 136 #ifdef CONFIG_PHYS_64BIT
 137 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 138 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 139 #else
 140 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 141 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 142 #endif
 143 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 144 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 145 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 146 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 147 #ifdef CONFIG_PHYS_64BIT
 148 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 149 #else
 150 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 151 #endif
 152
 153 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 154 #if defined(CONFIG_TARGET_P1010RDB_PA)
 155 #define CONFIG_SYS_PCIE2_NAME           "PCIe Slot"
 156 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 157 #define CONFIG_SYS_PCIE2_NAME           "mini PCIe Slot"
 158 #endif
 159 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 160 #ifdef CONFIG_PHYS_64BIT
 161 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 162 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 163 #else
 164 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 165 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 166 #endif
 167 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 168 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 169 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 170 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 171 #ifdef CONFIG_PHYS_64BIT
 172 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 173 #else
 174 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 175 #endif
 176
 177 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 178 #endif
 179
 180 #define CONFIG_ENV_OVERWRITE
 181
 182 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on P1010 RDB */
 183 #define CONFIG_SYS_CLK_FREQ     66666666 /* SYSCLK for P1010 RDB */
 184
 185 #define CONFIG_HWCONFIG
 186 /*
 187  * These can be toggled for performance analysis, otherwise use default.
 188  */
 189 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 190 #define CONFIG_BTB                      /* toggle branch predition */
 191
 192
 193 #define CONFIG_ENABLE_36BIT_PHYS
 194
 195 #ifdef CONFIG_PHYS_64BIT
 196 #define CONFIG_ADDR_MAP                 1
 197 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 198 #endif
 199
 200 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 201 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 202
 203 /* DDR Setup */
 204 #define CONFIG_SYS_DDR_RAW_TIMING
 205 #define CONFIG_DDR_SPD
 206 #define CONFIG_SYS_SPD_BUS_NUM          1
 207 #define SPD_EEPROM_ADDRESS              0x52
 208
 209 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 210
 211 #ifndef __ASSEMBLY__
 212 extern unsigned long get_sdram_size(void);
 213 #endif
 214 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 215 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 216 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 217
 218 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 219 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 220
 221 /* DDR3 Controller Settings */
 222 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 223 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 224 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 225 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 226 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 227 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 228 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 229 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 230 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 231 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 232 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 233 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
 234 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
 235 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 236 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 237
 238 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
 239 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
 240 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
 241 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
 242 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
 243 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
 244 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
 245 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
 246 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 247
 248 /* settings for DDR3 at 667MT/s */
 249 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
 250 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
 251 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
 252 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
 253 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
 254 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
 255 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
 256 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
 257 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
 258
 259 #define CONFIG_SYS_CCSRBAR                      0xffe00000
 260 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
 261
 262 /* Don't relocate CCSRBAR while in NAND_SPL */
 263 #ifdef CONFIG_SPL_BUILD
 264 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 265 #endif
 266
 267 /*
 268  * Memory map
 269  *
 270  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 271  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 272  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 273  *
 274  * Localbus non-cacheable
 275  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 276  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 277  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 278  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 279  */
 280
 281 /*
 282  * IFC Definitions
 283  */
 284 /* NOR Flash on IFC */
 285
 286 #define CONFIG_SYS_FLASH_BASE           0xee000000
 287 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 288
 289 #ifdef CONFIG_PHYS_64BIT
 290 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 291 #else
 292 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 293 #endif
 294
 295 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 296                                 CSPR_PORT_SIZE_16 | \
 297                                 CSPR_MSEL_NOR | \
 298                                 CSPR_V)
 299 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
 300 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
 301 /* NOR Flash Timing Params */
 302 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
 303                                 FTIM0_NOR_TEADC(0x5) | \
 304                                 FTIM0_NOR_TEAHC(0x5)
 305 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
 306                                 FTIM1_NOR_TRAD_NOR(0x0f)
 307 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
 308                                 FTIM2_NOR_TCH(0x4) | \
 309                                 FTIM2_NOR_TWP(0x1c)
 310 #define CONFIG_SYS_NOR_FTIM3    0x0
 311
 312 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 313 #define CONFIG_SYS_FLASH_QUIET_TEST
 314 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 315 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 316
 317 #undef CONFIG_SYS_FLASH_CHECKSUM
 318 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 319 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 320
 321 /* CFI for NOR Flash */
 322 #define CONFIG_SYS_FLASH_EMPTY_INFO
 323
 324 /* NAND Flash on IFC */
 325 #define CONFIG_SYS_NAND_BASE            0xff800000
 326 #ifdef CONFIG_PHYS_64BIT
 327 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 328 #else
 329 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 330 #endif
 331
 332 #define CONFIG_MTD_PARTITION
 333
 334 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 335                                 | CSPR_PORT_SIZE_8      \
 336                                 | CSPR_MSEL_NAND        \
 337                                 | CSPR_V)
 338 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 339
 340 #if defined(CONFIG_TARGET_P1010RDB_PA)
 341 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 342                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 343                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 344                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 345                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 346                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 347                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 348 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 349
 350 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 351 #define CONFIG_SYS_NAND_ONFI_DETECTION
 352 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 353                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 354                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 355                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 356                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 357                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 358                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 359 #define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
 360 #endif
 361
 362 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 363 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 364
 365 #if defined(CONFIG_TARGET_P1010RDB_PA)
 366 /* NAND Flash Timing Params */
 367 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
 368                                         FTIM0_NAND_TWP(0x0C)   | \
 369                                         FTIM0_NAND_TWCHT(0x04) | \
 370                                         FTIM0_NAND_TWH(0x05)
 371 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
 372                                         FTIM1_NAND_TWBE(0x1d)  | \
 373                                         FTIM1_NAND_TRR(0x07)   | \
 374                                         FTIM1_NAND_TRP(0x0c)
 375 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
 376                                         FTIM2_NAND_TREH(0x05) | \
 377                                         FTIM2_NAND_TWHRE(0x0f)
 378 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 379
 380 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 381 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 382 /* ONFI NAND Flash mode0 Timing Params */
 383 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 384                                         FTIM0_NAND_TWP(0x18)   | \
 385                                         FTIM0_NAND_TWCHT(0x07) | \
 386                                         FTIM0_NAND_TWH(0x0a))
 387 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 388                                         FTIM1_NAND_TWBE(0x39)  | \
 389                                         FTIM1_NAND_TRR(0x0e)   | \
 390                                         FTIM1_NAND_TRP(0x18))
 391 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 392                                         FTIM2_NAND_TREH(0x0a)  | \
 393                                         FTIM2_NAND_TWHRE(0x1e))
 394 #define CONFIG_SYS_NAND_FTIM3   0x0
 395 #endif
 396
 397 #define CONFIG_SYS_NAND_DDR_LAW         11
 398
 399 /* Set up IFC registers for boot location NOR/NAND */
 400 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
 401 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 402 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 403 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 404 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 405 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 406 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 407 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 408 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 409 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 410 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 411 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 412 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 413 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 414 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 415 #else
 416 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 417 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 418 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 419 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 420 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 421 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 422 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 423 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 424 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 425 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 426 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 427 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 428 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 429 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 430 #endif
 431
 432 /* CPLD on IFC */
 433 #define CONFIG_SYS_CPLD_BASE            0xffb00000
 434
 435 #ifdef CONFIG_PHYS_64BIT
 436 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
 437 #else
 438 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 439 #endif
 440
 441 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 442                                 | CSPR_PORT_SIZE_8 \
 443                                 | CSPR_MSEL_GPCM \
 444                                 | CSPR_V)
 445 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
 446 #define CONFIG_SYS_CSOR3                0x0
 447 /* CPLD Timing parameters for IFC CS3 */
 448 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 449                                         FTIM0_GPCM_TEADC(0x0e) | \
 450                                         FTIM0_GPCM_TEAHC(0x0e))
 451 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 452                                         FTIM1_GPCM_TRAD(0x1f))
 453 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 454                                         FTIM2_GPCM_TCH(0x8) | \
 455                                         FTIM2_GPCM_TWP(0x1f))
 456 #define CONFIG_SYS_CS3_FTIM3            0x0
 457
 458 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
 459         defined(CONFIG_RAMBOOT_NAND)
 460 #define CONFIG_SYS_RAMBOOT
 461 #else
 462 #undef CONFIG_SYS_RAMBOOT
 463 #endif
 464
 465 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 466 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
 467 #define CONFIG_A003399_NOR_WORKAROUND
 468 #endif
 469 #endif
 470
 471 #define CONFIG_SYS_INIT_RAM_LOCK
 472 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 473 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 474
 475 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 476                                                 - GENERATED_GBL_DATA_SIZE)
 477 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 478
 479 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 480 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 481
 482 /*
 483  * Config the L2 Cache as L2 SRAM
 484  */
 485 #if defined(CONFIG_SPL_BUILD)
 486 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 487 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 488 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 489 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 490 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 491 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 492 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 493 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 494 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (128 << 10)
 495 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
 496 #elif defined(CONFIG_NAND)
 497 #ifdef CONFIG_TPL_BUILD
 498 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 499 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 500 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 501 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 502 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 503 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 504 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 505 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 506 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 507 #else
 508 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 509 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 510 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 511 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 512 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
 513 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 514 #endif
 515 #endif
 516 #endif
 517
 518 /* Serial Port */
 519 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 520 #define CONFIG_SYS_NS16550_SERIAL
 521 #define CONFIG_SYS_NS16550_REG_SIZE     1
 522 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 523 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 524 #define CONFIG_NS16550_MIN_FUNCTIONS
 525 #endif
 526
 527 #define CONFIG_SYS_BAUDRATE_TABLE       \
 528         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 529
 530 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 531 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 532
 533 /* I2C */
 534 #define CONFIG_SYS_I2C
 535 #define CONFIG_SYS_I2C_FSL
 536 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 537 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 538 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 539 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 540 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 541 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 542 #define I2C_PCA9557_ADDR1               0x18
 543 #define I2C_PCA9557_ADDR2               0x19
 544 #define I2C_PCA9557_BUS_NUM             0
 545
 546 /* I2C EEPROM */
 547 #if defined(CONFIG_TARGET_P1010RDB_PB)
 548 #define CONFIG_ID_EEPROM
 549 #ifdef CONFIG_ID_EEPROM
 550 #define CONFIG_SYS_I2C_EEPROM_NXID
 551 #endif
 552 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 553 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 554 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 555 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 556 #endif
 557 /* enable read and write access to EEPROM */
 558 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 559 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 560 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 561
 562 /* RTC */
 563 #define CONFIG_RTC_PT7C4338
 564 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 565
 566 /*
 567  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 568  * used for SLIC
 569  */
 570 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
 571 /* eSPI - Enhanced SPI */
 572 #endif
 573
 574 #if defined(CONFIG_TSEC_ENET)
 575 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 576 #define CONFIG_TSEC1    1
 577 #define CONFIG_TSEC1_NAME       "eTSEC1"
 578 #define CONFIG_TSEC2    1
 579 #define CONFIG_TSEC2_NAME       "eTSEC2"
 580 #define CONFIG_TSEC3    1
 581 #define CONFIG_TSEC3_NAME       "eTSEC3"
 582
 583 #define TSEC1_PHY_ADDR          1
 584 #define TSEC2_PHY_ADDR          0
 585 #define TSEC3_PHY_ADDR          2
 586
 587 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 588 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 589 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 590
 591 #define TSEC1_PHYIDX            0
 592 #define TSEC2_PHYIDX            0
 593 #define TSEC3_PHYIDX            0
 594
 595 #define CONFIG_ETHPRIME         "eTSEC1"
 596
 597 /* TBI PHY configuration for SGMII mode */
 598 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 599                 TBICR_PHY_RESET \
 600                 | TBICR_ANEG_ENABLE \
 601                 | TBICR_FULL_DUPLEX \
 602                 | TBICR_SPEED1_SET \
 603                 )
 604
 605 #endif  /* CONFIG_TSEC_ENET */
 606
 607 /* SATA */
 608 #define CONFIG_FSL_SATA_V2
 609
 610 #ifdef CONFIG_FSL_SATA
 611 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 612 #define CONFIG_SATA1
 613 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 614 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 615 #define CONFIG_SATA2
 616 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 617 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 618
 619 #define CONFIG_LBA48
 620 #endif /* #ifdef CONFIG_FSL_SATA  */
 621
 622 #ifdef CONFIG_MMC
 623 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 624 #endif
 625
 626 #define CONFIG_HAS_FSL_DR_USB
 627
 628 #if defined(CONFIG_HAS_FSL_DR_USB)
 629 #ifdef CONFIG_USB_EHCI_HCD
 630 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 631 #define CONFIG_USB_EHCI_FSL
 632 #endif
 633 #endif
 634
 635 /*
 636  * Environment
 637  */
 638 #if defined(CONFIG_SDCARD)
 639 #define CONFIG_FSL_FIXED_MMC_LOCATION
 640 #define CONFIG_SYS_MMC_ENV_DEV          0
 641 #define CONFIG_ENV_SIZE                 0x2000
 642 #elif defined(CONFIG_SPIFLASH)
 643 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 644 #define CONFIG_ENV_SECT_SIZE    0x10000
 645 #define CONFIG_ENV_SIZE         0x2000
 646 #elif defined(CONFIG_NAND)
 647 #ifdef CONFIG_TPL_BUILD
 648 #define CONFIG_ENV_SIZE         0x2000
 649 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 650 #else
 651 #if defined(CONFIG_TARGET_P1010RDB_PA)
 652 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 653 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
 654 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 655 #define CONFIG_ENV_SIZE         (16 * 1024)
 656 #define CONFIG_ENV_RANGE        (32 * CONFIG_ENV_SIZE) /* new block size 512K */
 657 #endif
 658 #endif
 659 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 660 #elif defined(CONFIG_SYS_RAMBOOT)
 661 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - 0x1000)
 662 #define CONFIG_ENV_SIZE                 0x2000
 663 #else
 664 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 665 #define CONFIG_ENV_SIZE         0x2000
 666 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 667 #endif
 668
 669 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 670 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 671
 672 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 673
 674 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
 675                  || defined(CONFIG_FSL_SATA)
 676 #endif
 677
 678 /*
 679  * Miscellaneous configurable options
 680  */
 681 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 682
 683 /*
 684  * For booting Linux, the board info and command line data
 685  * have to be in the first 64 MB of memory, since this is
 686  * the maximum mapped by the Linux kernel during initialization.
 687  */
 688 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 689 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 690
 691 #if defined(CONFIG_CMD_KGDB)
 692 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 693 #endif
 694
 695 /*
 696  * Environment Configuration
 697  */
 698
 699 #if defined(CONFIG_TSEC_ENET)
 700 #define CONFIG_HAS_ETH0
 701 #define CONFIG_HAS_ETH1
 702 #define CONFIG_HAS_ETH2
 703 #endif
 704
 705 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 706 #define CONFIG_BOOTFILE         "uImage"
 707 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 708
 709 /* default location for tftp and bootm */
 710 #define CONFIG_LOADADDR         1000000
 711
 712 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 713         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 714         "netdev=eth0\0"                                         \
 715         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 716         "loadaddr=1000000\0"                    \
 717         "consoledev=ttyS0\0"                            \
 718         "ramdiskaddr=2000000\0"                 \
 719         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 720         "fdtaddr=1e00000\0"                             \
 721         "fdtfile=p1010rdb.dtb\0"                \
 722         "bdev=sda1\0"   \
 723         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 724         "othbootargs=ramdisk_size=600000\0" \
 725         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 726         "console=$consoledev,$baudrate $othbootargs; "  \
 727         "usb start;"                    \
 728         "fatload usb 0:2 $loadaddr $bootfile;"          \
 729         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 730         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 731         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 732         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 733         "console=$consoledev,$baudrate $othbootargs; "  \
 734         "usb start;"                    \
 735         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 736         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 737         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 738         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 739         CONFIG_BOOTMODE
 740
 741 #if defined(CONFIG_TARGET_P1010RDB_PA)
 742 #define CONFIG_BOOTMODE \
 743         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 744         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 745         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 746         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 747         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 748         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 749
 750 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 751 #define CONFIG_BOOTMODE \
 752         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 753         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 754         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 755         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 756         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 757         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 758         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 759         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 760         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 761         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 762 #endif
 763
 764 #define CONFIG_RAMBOOTCOMMAND           \
 765         "setenv bootargs root=/dev/ram rw "     \
 766         "console=$consoledev,$baudrate $othbootargs; "  \
 767         "tftp $ramdiskaddr $ramdiskfile;"       \
 768         "tftp $loadaddr $bootfile;"             \
 769         "tftp $fdtaddr $fdtfile;"               \
 770         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 771
 772 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 773
 774 #include <asm/fsl_secure_boot.h>
 775
 776 #endif  /* __CONFIG_H */