1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * P010 RDB board configuration file
14 #include <linux/stringify.h>
16 #include <asm/config_mpc85xx.h>
19 #define CFG_SYS_MMC_U_BOOT_SIZE (512 << 10)
20 #define CFG_SYS_MMC_U_BOOT_DST (0x11000000)
21 #define CFG_SYS_MMC_U_BOOT_START (0x11000000)
22 #define CFG_SYS_MMC_U_BOOT_OFFS (96 << 10)
25 #ifdef CONFIG_SPIFLASH
26 #ifdef CONFIG_NXP_ESBC
27 #define CONFIG_RAMBOOT_SPIFLASH
28 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
30 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
31 #define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
32 #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
33 #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
37 #ifdef CONFIG_MTD_RAW_NAND
38 #ifdef CONFIG_NXP_ESBC
39 #define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
40 #define CFG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
41 #define CFG_SYS_NAND_U_BOOT_START 0x00200000
43 #ifdef CONFIG_TPL_BUILD
44 #define CFG_SYS_NAND_U_BOOT_SIZE (576 << 10)
45 #define CFG_SYS_NAND_U_BOOT_DST (0x11000000)
46 #define CFG_SYS_NAND_U_BOOT_START (0x11000000)
47 #elif defined(CONFIG_SPL_BUILD)
48 #define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10)
49 #define CFG_SYS_NAND_U_BOOT_DST 0xD0000000
50 #define CFG_SYS_NAND_U_BOOT_START 0xD0000000
55 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
56 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
59 #ifndef CONFIG_RESET_VECTOR_ADDRESS
60 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
63 /* High Level Configuration Options */
65 #if defined(CONFIG_PCI)
68 * Memory space is mapped 1-1, but I/O space must start from 0.
70 /* controller 1, Slot 1, tgtid 1, Base address a000 */
71 #define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
72 #ifdef CONFIG_PHYS_64BIT
73 #define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
75 #define CFG_SYS_PCIE1_MEM_PHYS 0x80000000
77 #define CFG_SYS_PCIE1_IO_VIRT 0xffc00000
78 #ifdef CONFIG_PHYS_64BIT
79 #define CFG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
81 #define CFG_SYS_PCIE1_IO_PHYS 0xffc00000
84 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
85 #define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
86 #ifdef CONFIG_PHYS_64BIT
87 #define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
89 #define CFG_SYS_PCIE2_MEM_PHYS 0xa0000000
91 #define CFG_SYS_PCIE2_IO_VIRT 0xffc10000
92 #ifdef CONFIG_PHYS_64BIT
93 #define CFG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
95 #define CFG_SYS_PCIE2_IO_PHYS 0xffc10000
100 * These can be toggled for performance analysis, otherwise use default.
102 #define CONFIG_L2_CACHE /* toggle L2 cache */
105 #define SPD_EEPROM_ADDRESS 0x52
107 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
110 extern unsigned long get_sdram_size(void);
112 #define CFG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
113 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000
114 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
116 #define CFG_SYS_CCSRBAR 0xffe00000
117 #define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
122 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
123 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
124 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
126 * Localbus non-cacheable
127 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
128 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
129 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
130 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
136 /* NOR Flash on IFC */
138 #define CFG_SYS_FLASH_BASE 0xee000000
140 #ifdef CONFIG_PHYS_64BIT
141 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
143 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
146 #define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
147 CSPR_PORT_SIZE_16 | \
150 #define CFG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
151 #define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
152 /* NOR Flash Timing Params */
153 #define CFG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
154 FTIM0_NOR_TEADC(0x5) | \
156 #define CFG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
157 FTIM1_NOR_TRAD_NOR(0x0f)
158 #define CFG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
159 FTIM2_NOR_TCH(0x4) | \
161 #define CFG_SYS_NOR_FTIM3 0x0
163 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
164 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
166 /* CFI for NOR Flash */
168 /* NAND Flash on IFC */
169 #define CFG_SYS_NAND_BASE 0xff800000
170 #ifdef CONFIG_PHYS_64BIT
171 #define CFG_SYS_NAND_BASE_PHYS 0xfff800000ull
173 #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
176 #define CONFIG_MTD_PARTITION
178 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
182 #define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
184 #if defined(CONFIG_TARGET_P1010RDB_PA)
185 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
186 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
187 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
188 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
189 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
190 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
191 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
193 #elif defined(CONFIG_TARGET_P1010RDB_PB)
194 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
195 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
196 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
197 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
198 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
199 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
200 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
203 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
205 #if defined(CONFIG_TARGET_P1010RDB_PA)
206 /* NAND Flash Timing Params */
207 #define CFG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
208 FTIM0_NAND_TWP(0x0C) | \
209 FTIM0_NAND_TWCHT(0x04) | \
211 #define CFG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
212 FTIM1_NAND_TWBE(0x1d) | \
213 FTIM1_NAND_TRR(0x07) | \
215 #define CFG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
216 FTIM2_NAND_TREH(0x05) | \
217 FTIM2_NAND_TWHRE(0x0f)
218 #define CFG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
220 #elif defined(CONFIG_TARGET_P1010RDB_PB)
221 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
222 /* ONFI NAND Flash mode0 Timing Params */
223 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
224 FTIM0_NAND_TWP(0x18) | \
225 FTIM0_NAND_TWCHT(0x07) | \
226 FTIM0_NAND_TWH(0x0a))
227 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
228 FTIM1_NAND_TWBE(0x39) | \
229 FTIM1_NAND_TRR(0x0e) | \
230 FTIM1_NAND_TRP(0x18))
231 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
232 FTIM2_NAND_TREH(0x0a) | \
233 FTIM2_NAND_TWHRE(0x1e))
234 #define CFG_SYS_NAND_FTIM3 0x0
237 /* Set up IFC registers for boot location NOR/NAND */
238 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
239 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
240 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
241 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
242 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
243 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
244 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
245 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
246 #define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR
247 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
248 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
249 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
250 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
251 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
252 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
254 #define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
255 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
256 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
257 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
258 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
259 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
260 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
261 #define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
262 #define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
263 #define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
264 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
265 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
266 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
267 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
271 #define CFG_SYS_CPLD_BASE 0xffb00000
273 #ifdef CONFIG_PHYS_64BIT
274 #define CFG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
276 #define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
279 #define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
283 #define CFG_SYS_AMASK3 IFC_AMASK(64*1024)
284 #define CFG_SYS_CSOR3 0x0
285 /* CPLD Timing parameters for IFC CS3 */
286 #define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
287 FTIM0_GPCM_TEADC(0x0e) | \
288 FTIM0_GPCM_TEAHC(0x0e))
289 #define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
290 FTIM1_GPCM_TRAD(0x1f))
291 #define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
292 FTIM2_GPCM_TCH(0x8) | \
293 FTIM2_GPCM_TWP(0x1f))
294 #define CFG_SYS_CS3_FTIM3 0x0
296 #define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
297 #define CFG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
299 #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
302 * Config the L2 Cache as L2 SRAM
304 #if defined(CONFIG_SPL_BUILD)
305 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
306 #define CFG_SYS_INIT_L2_ADDR 0xD0000000
307 #define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
308 #define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
309 #elif defined(CONFIG_MTD_RAW_NAND)
310 #ifdef CONFIG_TPL_BUILD
311 #define CFG_SYS_INIT_L2_ADDR 0xD0000000
312 #define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
313 #define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
315 #define CFG_SYS_INIT_L2_ADDR 0xD0000000
316 #define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
317 #define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
323 #undef CONFIG_SERIAL_SOFTWARE_FIFO
324 #define CFG_SYS_NS16550_CLK get_bus_freq(0)
326 #define CFG_SYS_BAUDRATE_TABLE \
327 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
329 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500)
330 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
333 #define I2C_PCA9557_ADDR1 0x18
334 #define I2C_PCA9557_ADDR2 0x19
335 #define I2C_PCA9557_BUS_NUM 0
338 #if defined(CONFIG_TARGET_P1010RDB_PB)
339 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
341 /* enable read and write access to EEPROM */
344 #define CFG_SYS_I2C_RTC_ADDR 0x68
347 * SPI interface will not be available in case of NAND boot SPI CS0 will be
350 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
351 /* eSPI - Enhanced SPI */
354 #if defined(CONFIG_TSEC_ENET)
355 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
356 #define CONFIG_TSEC1 1
357 #define CONFIG_TSEC1_NAME "eTSEC1"
358 #define CONFIG_TSEC2 1
359 #define CONFIG_TSEC2_NAME "eTSEC2"
360 #define CONFIG_TSEC3 1
361 #define CONFIG_TSEC3_NAME "eTSEC3"
363 #define TSEC1_PHY_ADDR 1
364 #define TSEC2_PHY_ADDR 0
365 #define TSEC3_PHY_ADDR 2
367 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
368 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
369 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
371 #define TSEC1_PHYIDX 0
372 #define TSEC2_PHYIDX 0
373 #define TSEC3_PHYIDX 0
375 /* TBI PHY configuration for SGMII mode */
376 #define CONFIG_TSEC_TBICR_SETTINGS ( \
378 | TBICR_ANEG_ENABLE \
379 | TBICR_FULL_DUPLEX \
383 #endif /* CONFIG_TSEC_ENET */
386 #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
392 #if defined(CONFIG_MTD_RAW_NAND)
393 #ifdef CONFIG_TPL_BUILD
394 #define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10))
398 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
399 || defined(CONFIG_FSL_SATA)
403 * Miscellaneous configurable options
407 * For booting Linux, the board info and command line data
408 * have to be in the first 64 MB of memory, since this is
409 * the maximum mapped by the Linux kernel during initialization.
411 #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
414 * Environment Configuration
417 #define CONFIG_ROOTPATH "/opt/nfsroot"
418 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
420 #define CONFIG_EXTRA_ENV_SETTINGS \
421 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
423 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
424 "loadaddr=1000000\0" \
425 "consoledev=ttyS0\0" \
426 "ramdiskaddr=2000000\0" \
427 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
428 "fdtaddr=1e00000\0" \
429 "fdtfile=p1010rdb.dtb\0" \
431 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
432 "othbootargs=ramdisk_size=600000\0" \
433 "usbfatboot=setenv bootargs root=/dev/ram rw " \
434 "console=$consoledev,$baudrate $othbootargs; " \
436 "fatload usb 0:2 $loadaddr $bootfile;" \
437 "fatload usb 0:2 $fdtaddr $fdtfile;" \
438 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
439 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
440 "usbext2boot=setenv bootargs root=/dev/ram rw " \
441 "console=$consoledev,$baudrate $othbootargs; " \
443 "ext2load usb 0:4 $loadaddr $bootfile;" \
444 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
445 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
446 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
449 #if defined(CONFIG_TARGET_P1010RDB_PA)
451 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
452 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
453 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
454 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
455 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
456 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
458 #elif defined(CONFIG_TARGET_P1010RDB_PB)
460 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
461 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
462 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
463 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
464 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
465 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
466 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
467 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
468 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
469 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
472 #include <asm/fsl_secure_boot.h>
474 #endif /* __CONFIG_H */