include/configs/P1010RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * P010 RDB board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include <linux/stringify.h>
  15
  16 #include <asm/config_mpc85xx.h>
  17
  18 #ifdef CONFIG_SDCARD
  19 #define CFG_SYS_MMC_U_BOOT_SIZE (512 << 10)
  20 #define CFG_SYS_MMC_U_BOOT_DST  (0x11000000)
  21 #define CFG_SYS_MMC_U_BOOT_START        (0x11000000)
  22 #define CFG_SYS_MMC_U_BOOT_OFFS (96 << 10)
  23 #endif
  24
  25 #ifdef CONFIG_SPIFLASH
  26 #ifdef CONFIG_NXP_ESBC
  27 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  28 #else
  29 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE   (512 << 10)
  30 #define CFG_SYS_SPI_FLASH_U_BOOT_DST            (0x11000000)
  31 #define CFG_SYS_SPI_FLASH_U_BOOT_START  (0x11000000)
  32 #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS   (96 << 10)
  33 #endif
  34 #endif
  35
  36 #ifdef CONFIG_MTD_RAW_NAND
  37 #ifdef CONFIG_NXP_ESBC
  38 #define CFG_SYS_NAND_U_BOOT_SIZE        ((768 << 10) - 0x2000)
  39 #define CFG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
  40 #define CFG_SYS_NAND_U_BOOT_START       0x00200000
  41 #else
  42 #ifdef CONFIG_TPL_BUILD
  43 #define CFG_SYS_NAND_U_BOOT_SIZE        (576 << 10)
  44 #define CFG_SYS_NAND_U_BOOT_DST (0x11000000)
  45 #define CFG_SYS_NAND_U_BOOT_START       (0x11000000)
  46 #elif defined(CONFIG_SPL_BUILD)
  47 #define CFG_SYS_NAND_U_BOOT_SIZE        (128 << 10)
  48 #define CFG_SYS_NAND_U_BOOT_DST 0xD0000000
  49 #define CFG_SYS_NAND_U_BOOT_START       0xD0000000
  50 #endif
  51 #endif
  52 #endif
  53
  54 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
  55 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  56 #endif
  57
  58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  59 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  60 #endif
  61
  62 /* High Level Configuration Options */
  63
  64 #if defined(CONFIG_PCI)
  65 /*
  66  * PCI Windows
  67  * Memory space is mapped 1-1, but I/O space must start from 0.
  68  */
  69 /* controller 1, Slot 1, tgtid 1, Base address a000 */
  70 #define CFG_SYS_PCIE1_MEM_VIRT  0x80000000
  71 #ifdef CONFIG_PHYS_64BIT
  72 #define CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
  73 #else
  74 #define CFG_SYS_PCIE1_MEM_PHYS  0x80000000
  75 #endif
  76 #define CFG_SYS_PCIE1_IO_VIRT   0xffc00000
  77 #ifdef CONFIG_PHYS_64BIT
  78 #define CFG_SYS_PCIE1_IO_PHYS   0xfffc00000ull
  79 #else
  80 #define CFG_SYS_PCIE1_IO_PHYS   0xffc00000
  81 #endif
  82
  83 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
  84 #define CFG_SYS_PCIE2_MEM_VIRT  0xa0000000
  85 #ifdef CONFIG_PHYS_64BIT
  86 #define CFG_SYS_PCIE2_MEM_PHYS  0xc20000000ull
  87 #else
  88 #define CFG_SYS_PCIE2_MEM_PHYS  0xa0000000
  89 #endif
  90 #define CFG_SYS_PCIE2_IO_VIRT   0xffc10000
  91 #ifdef CONFIG_PHYS_64BIT
  92 #define CFG_SYS_PCIE2_IO_PHYS   0xfffc10000ull
  93 #else
  94 #define CFG_SYS_PCIE2_IO_PHYS   0xffc10000
  95 #endif
  96 #endif
  97
  98 /* DDR Setup */
  99 #define SPD_EEPROM_ADDRESS              0x52
 100
 101 #ifndef __ASSEMBLY__
 102 extern unsigned long get_sdram_size(void);
 103 #endif
 104 #define CFG_SYS_SDRAM_SIZE              get_sdram_size() /* DDR size */
 105 #define CFG_SYS_DDR_SDRAM_BASE  0x00000000
 106 #define CFG_SYS_SDRAM_BASE              CFG_SYS_DDR_SDRAM_BASE
 107
 108 #define CFG_SYS_CCSRBAR                 0xffe00000
 109 #define CFG_SYS_CCSRBAR_PHYS_LOW                CFG_SYS_CCSRBAR
 110
 111 /*
 112  * Memory map
 113  *
 114  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 115  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 116  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 117  *
 118  * Localbus non-cacheable
 119  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 120  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 121  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 122  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 123  */
 124
 125 /*
 126  * IFC Definitions
 127  */
 128 /* NOR Flash on IFC */
 129
 130 #define CFG_SYS_FLASH_BASE              0xee000000
 131
 132 #ifdef CONFIG_PHYS_64BIT
 133 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
 134 #else
 135 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
 136 #endif
 137
 138 #define CFG_SYS_NOR_CSPR        (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
 139                                 CSPR_PORT_SIZE_16 | \
 140                                 CSPR_MSEL_NOR | \
 141                                 CSPR_V)
 142 #define CFG_SYS_NOR_AMASK       IFC_AMASK(32*1024*1024)
 143 #define CFG_SYS_NOR_CSOR        CSOR_NOR_ADM_SHIFT(7)
 144 /* NOR Flash Timing Params */
 145 #define CFG_SYS_NOR_FTIM0       FTIM0_NOR_TACSE(0x4) | \
 146                                 FTIM0_NOR_TEADC(0x5) | \
 147                                 FTIM0_NOR_TEAHC(0x5)
 148 #define CFG_SYS_NOR_FTIM1       FTIM1_NOR_TACO(0x1e) | \
 149                                 FTIM1_NOR_TRAD_NOR(0x0f)
 150 #define CFG_SYS_NOR_FTIM2       FTIM2_NOR_TCS(0x4) | \
 151                                 FTIM2_NOR_TCH(0x4) | \
 152                                 FTIM2_NOR_TWP(0x1c)
 153 #define CFG_SYS_NOR_FTIM3       0x0
 154
 155 #define CFG_SYS_FLASH_BANKS_LIST        {CFG_SYS_FLASH_BASE_PHYS}
 156
 157 /* CFI for NOR Flash */
 158
 159 /* NAND Flash on IFC */
 160 #define CFG_SYS_NAND_BASE               0xff800000
 161 #ifdef CONFIG_PHYS_64BIT
 162 #define CFG_SYS_NAND_BASE_PHYS  0xfff800000ull
 163 #else
 164 #define CFG_SYS_NAND_BASE_PHYS  CFG_SYS_NAND_BASE
 165 #endif
 166
 167 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 168                                 | CSPR_PORT_SIZE_8      \
 169                                 | CSPR_MSEL_NAND        \
 170                                 | CSPR_V)
 171 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
 172
 173 #if defined(CONFIG_TARGET_P1010RDB_PA)
 174 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 175                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 176                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 177                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 178                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 179                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 180                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 181
 182 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 183 #define CFG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 184                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 185                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 186                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 187                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 188                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 189                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 190 #endif
 191
 192 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 193
 194 #if defined(CONFIG_TARGET_P1010RDB_PA)
 195 /* NAND Flash Timing Params */
 196 #define CFG_SYS_NAND_FTIM0              FTIM0_NAND_TCCST(0x01) | \
 197                                         FTIM0_NAND_TWP(0x0C)   | \
 198                                         FTIM0_NAND_TWCHT(0x04) | \
 199                                         FTIM0_NAND_TWH(0x05)
 200 #define CFG_SYS_NAND_FTIM1              FTIM1_NAND_TADLE(0x1d) | \
 201                                         FTIM1_NAND_TWBE(0x1d)  | \
 202                                         FTIM1_NAND_TRR(0x07)   | \
 203                                         FTIM1_NAND_TRP(0x0c)
 204 #define CFG_SYS_NAND_FTIM2              FTIM2_NAND_TRAD(0x0c) | \
 205                                         FTIM2_NAND_TREH(0x05) | \
 206                                         FTIM2_NAND_TWHRE(0x0f)
 207 #define CFG_SYS_NAND_FTIM3              FTIM3_NAND_TWW(0x04)
 208
 209 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 210 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 211 /* ONFI NAND Flash mode0 Timing Params */
 212 #define CFG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 213                                         FTIM0_NAND_TWP(0x18)   | \
 214                                         FTIM0_NAND_TWCHT(0x07) | \
 215                                         FTIM0_NAND_TWH(0x0a))
 216 #define CFG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 217                                         FTIM1_NAND_TWBE(0x39)  | \
 218                                         FTIM1_NAND_TRR(0x0e)   | \
 219                                         FTIM1_NAND_TRP(0x18))
 220 #define CFG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 221                                         FTIM2_NAND_TREH(0x0a)  | \
 222                                         FTIM2_NAND_TWHRE(0x1e))
 223 #define CFG_SYS_NAND_FTIM3      0x0
 224 #endif
 225
 226 /* Set up IFC registers for boot location NOR/NAND */
 227 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
 228 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 229 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 230 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 231 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 232 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 233 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 234 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 235 #define CFG_SYS_CSPR1           CFG_SYS_NOR_CSPR
 236 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 237 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 238 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 239 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 240 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 241 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 242 #else
 243 #define CFG_SYS_CSPR0           CFG_SYS_NOR_CSPR
 244 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 245 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 246 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 247 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 248 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 249 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 250 #define CFG_SYS_CSPR1           CFG_SYS_NAND_CSPR
 251 #define CFG_SYS_AMASK1          CFG_SYS_NAND_AMASK
 252 #define CFG_SYS_CSOR1           CFG_SYS_NAND_CSOR
 253 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NAND_FTIM0
 254 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NAND_FTIM1
 255 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NAND_FTIM2
 256 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NAND_FTIM3
 257 #endif
 258
 259 /* CPLD on IFC */
 260 #define CFG_SYS_CPLD_BASE               0xffb00000
 261
 262 #ifdef CONFIG_PHYS_64BIT
 263 #define CFG_SYS_CPLD_BASE_PHYS  0xfffb00000ull
 264 #else
 265 #define CFG_SYS_CPLD_BASE_PHYS  CFG_SYS_CPLD_BASE
 266 #endif
 267
 268 #define CFG_SYS_CSPR3   (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
 269                                 | CSPR_PORT_SIZE_8 \
 270                                 | CSPR_MSEL_GPCM \
 271                                 | CSPR_V)
 272 #define CFG_SYS_AMASK3          IFC_AMASK(64*1024)
 273 #define CFG_SYS_CSOR3           0x0
 274 /* CPLD Timing parameters for IFC CS3 */
 275 #define CFG_SYS_CS3_FTIM0               (FTIM0_GPCM_TACSE(0x0e) | \
 276                                         FTIM0_GPCM_TEADC(0x0e) | \
 277                                         FTIM0_GPCM_TEAHC(0x0e))
 278 #define CFG_SYS_CS3_FTIM1               (FTIM1_GPCM_TACO(0x0e) | \
 279                                         FTIM1_GPCM_TRAD(0x1f))
 280 #define CFG_SYS_CS3_FTIM2               (FTIM2_GPCM_TCS(0x0e) | \
 281                                         FTIM2_GPCM_TCH(0x8) | \
 282                                         FTIM2_GPCM_TWP(0x1f))
 283 #define CFG_SYS_CS3_FTIM3               0x0
 284
 285 #define CFG_SYS_INIT_RAM_ADDR   0xffd00000 /* stack in RAM */
 286 #define CFG_SYS_INIT_RAM_SIZE   0x00004000 /* End of used area in RAM */
 287
 288 #define CFG_SYS_INIT_SP_OFFSET  (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 289
 290 /*
 291  * Config the L2 Cache as L2 SRAM
 292  */
 293 #if defined(CONFIG_SPL_BUILD)
 294 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 295 #define CFG_SYS_INIT_L2_ADDR            0xD0000000
 296 #define CFG_SYS_INIT_L2_ADDR_PHYS       CFG_SYS_INIT_L2_ADDR
 297 #define CFG_SYS_INIT_L2_END     (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 298 #elif defined(CONFIG_MTD_RAW_NAND)
 299 #ifdef CONFIG_TPL_BUILD
 300 #define CFG_SYS_INIT_L2_ADDR            0xD0000000
 301 #define CFG_SYS_INIT_L2_ADDR_PHYS       CFG_SYS_INIT_L2_ADDR
 302 #define CFG_SYS_INIT_L2_END     (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 303 #else
 304 #define CFG_SYS_INIT_L2_ADDR            0xD0000000
 305 #define CFG_SYS_INIT_L2_ADDR_PHYS       CFG_SYS_INIT_L2_ADDR
 306 #define CFG_SYS_INIT_L2_END     (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 307 #endif
 308 #endif
 309 #endif
 310
 311 /* Serial Port */
 312 #define CFG_SYS_NS16550_CLK             get_bus_freq(0)
 313
 314 #define CFG_SYS_BAUDRATE_TABLE  \
 315         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 316
 317 #define CFG_SYS_NS16550_COM1    (CFG_SYS_CCSRBAR+0x4500)
 318 #define CFG_SYS_NS16550_COM2    (CFG_SYS_CCSRBAR+0x4600)
 319
 320 /* I2C */
 321 #define I2C_PCA9557_ADDR1               0x18
 322 #define I2C_PCA9557_ADDR2               0x19
 323 #define I2C_PCA9557_BUS_NUM             0
 324
 325 /* I2C EEPROM */
 326 #if defined(CONFIG_TARGET_P1010RDB_PB)
 327 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 328 #endif
 329 /* enable read and write access to EEPROM */
 330
 331 /* RTC */
 332 #define CFG_SYS_I2C_RTC_ADDR    0x68
 333
 334 /*
 335  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 336  * used for SLIC
 337  */
 338 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
 339 /* eSPI - Enhanced SPI */
 340 #endif
 341
 342 #ifdef CONFIG_MMC
 343 #define CFG_SYS_FSL_ESDHC_ADDR  CFG_SYS_MPC85xx_ESDHC_ADDR
 344 #endif
 345
 346 /*
 347  * Environment
 348  */
 349 #if defined(CONFIG_MTD_RAW_NAND)
 350 #ifdef CONFIG_TPL_BUILD
 351 #define SPL_ENV_ADDR            (CFG_SYS_INIT_L2_ADDR + (160 << 10))
 352 #endif
 353 #endif
 354
 355 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
 356                  || defined(CONFIG_FSL_SATA)
 357 #endif
 358
 359 /*
 360  * Miscellaneous configurable options
 361  */
 362
 363 /*
 364  * For booting Linux, the board info and command line data
 365  * have to be in the first 64 MB of memory, since this is
 366  * the maximum mapped by the Linux kernel during initialization.
 367  */
 368 #define CFG_SYS_BOOTMAPSZ       (64 << 20) /* Initial Memory map for Linux */
 369
 370 /*
 371  * Environment Configuration
 372  */
 373
 374 #define CFG_EXTRA_ENV_SETTINGS                          \
 375         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 376         "netdev=eth0\0"                                         \
 377         "uboot=" CONFIG_UBOOTPATH "\0"          \
 378         "loadaddr=1000000\0"                    \
 379         "consoledev=ttyS0\0"                            \
 380         "ramdiskaddr=2000000\0"                 \
 381         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 382         "fdtaddr=1e00000\0"                             \
 383         "fdtfile=p1010rdb.dtb\0"                \
 384         "bdev=sda1\0"   \
 385         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 386         "othbootargs=ramdisk_size=600000\0" \
 387         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 388         "console=$consoledev,$baudrate $othbootargs; "  \
 389         "usb start;"                    \
 390         "fatload usb 0:2 $loadaddr $bootfile;"          \
 391         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 392         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 393         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 394         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 395         "console=$consoledev,$baudrate $othbootargs; "  \
 396         "usb start;"                    \
 397         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 398         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 399         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 400         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 401         BOOTMODE
 402
 403 #if defined(CONFIG_TARGET_P1010RDB_PA)
 404 #define BOOTMODE \
 405         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 406         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 407         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 408         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 409         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 410         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 411
 412 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 413 #define BOOTMODE \
 414         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 415         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 416         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 417         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 418         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 419         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 420         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 421         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 422         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 423         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 424 #endif
 425
 426 #include <asm/fsl_secure_boot.h>
 427
 428 #endif  /* __CONFIG_H */