1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * P010 RDB board configuration file
14 #include <linux/stringify.h>
16 #include <asm/config_mpc85xx.h>
19 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
20 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
21 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
22 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
25 #ifdef CONFIG_SPIFLASH
26 #ifdef CONFIG_NXP_ESBC
27 #define CONFIG_RAMBOOT_SPIFLASH
28 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
30 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
31 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
32 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
33 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
37 #ifdef CONFIG_MTD_RAW_NAND
38 #ifdef CONFIG_NXP_ESBC
39 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
40 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
41 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
43 #ifdef CONFIG_TPL_BUILD
44 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
45 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
46 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
47 #elif defined(CONFIG_SPL_BUILD)
48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
49 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
50 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
55 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
56 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
59 #ifndef CONFIG_RESET_VECTOR_ADDRESS
60 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
63 /* High Level Configuration Options */
65 #if defined(CONFIG_PCI)
66 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
67 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
71 * Memory space is mapped 1-1, but I/O space must start from 0.
73 /* controller 1, Slot 1, tgtid 1, Base address a000 */
74 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
75 #ifdef CONFIG_PHYS_64BIT
76 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
78 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
80 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
81 #ifdef CONFIG_PHYS_64BIT
82 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
84 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
87 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
88 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
89 #ifdef CONFIG_PHYS_64BIT
90 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
92 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
94 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
95 #ifdef CONFIG_PHYS_64BIT
96 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
98 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
101 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
104 #define CONFIG_HWCONFIG
106 * These can be toggled for performance analysis, otherwise use default.
108 #define CONFIG_L2_CACHE /* toggle L2 cache */
111 #define SPD_EEPROM_ADDRESS 0x52
113 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
116 extern unsigned long get_sdram_size(void);
118 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
119 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
120 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
122 /* DDR3 Controller Settings */
123 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
124 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
125 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
126 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
127 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
128 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
129 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
130 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
131 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
132 #define CONFIG_SYS_DDR_RCW_1 0x00000000
133 #define CONFIG_SYS_DDR_RCW_2 0x00000000
134 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
135 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
136 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
137 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
139 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
140 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
141 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
142 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
143 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
144 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
145 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
146 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
147 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
149 /* settings for DDR3 at 667MT/s */
150 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
151 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
152 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
153 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
154 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
155 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
156 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
157 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
158 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
160 #define CONFIG_SYS_CCSRBAR 0xffe00000
161 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
166 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
167 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
168 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
170 * Localbus non-cacheable
171 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
172 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
173 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
174 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
180 /* NOR Flash on IFC */
182 #define CONFIG_SYS_FLASH_BASE 0xee000000
183 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
185 #ifdef CONFIG_PHYS_64BIT
186 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
188 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
191 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
192 CSPR_PORT_SIZE_16 | \
195 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
196 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
197 /* NOR Flash Timing Params */
198 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
199 FTIM0_NOR_TEADC(0x5) | \
201 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
202 FTIM1_NOR_TRAD_NOR(0x0f)
203 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
204 FTIM2_NOR_TCH(0x4) | \
206 #define CONFIG_SYS_NOR_FTIM3 0x0
208 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
209 #define CONFIG_SYS_FLASH_QUIET_TEST
210 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
212 #undef CONFIG_SYS_FLASH_CHECKSUM
213 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
214 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
216 /* CFI for NOR Flash */
217 #define CONFIG_SYS_FLASH_EMPTY_INFO
219 /* NAND Flash on IFC */
220 #define CONFIG_SYS_NAND_BASE 0xff800000
221 #ifdef CONFIG_PHYS_64BIT
222 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
224 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
227 #define CONFIG_MTD_PARTITION
229 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
233 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
235 #if defined(CONFIG_TARGET_P1010RDB_PA)
236 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
237 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
238 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
239 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
240 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
241 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
242 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
244 #elif defined(CONFIG_TARGET_P1010RDB_PB)
245 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
246 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
247 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
248 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
249 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
250 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
251 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
254 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
255 #define CONFIG_SYS_MAX_NAND_DEVICE 1
257 #if defined(CONFIG_TARGET_P1010RDB_PA)
258 /* NAND Flash Timing Params */
259 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
260 FTIM0_NAND_TWP(0x0C) | \
261 FTIM0_NAND_TWCHT(0x04) | \
263 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
264 FTIM1_NAND_TWBE(0x1d) | \
265 FTIM1_NAND_TRR(0x07) | \
267 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
268 FTIM2_NAND_TREH(0x05) | \
269 FTIM2_NAND_TWHRE(0x0f)
270 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
272 #elif defined(CONFIG_TARGET_P1010RDB_PB)
273 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
274 /* ONFI NAND Flash mode0 Timing Params */
275 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
276 FTIM0_NAND_TWP(0x18) | \
277 FTIM0_NAND_TWCHT(0x07) | \
278 FTIM0_NAND_TWH(0x0a))
279 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
280 FTIM1_NAND_TWBE(0x39) | \
281 FTIM1_NAND_TRR(0x0e) | \
282 FTIM1_NAND_TRP(0x18))
283 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
284 FTIM2_NAND_TREH(0x0a) | \
285 FTIM2_NAND_TWHRE(0x1e))
286 #define CONFIG_SYS_NAND_FTIM3 0x0
289 #define CONFIG_SYS_NAND_DDR_LAW 11
291 /* Set up IFC registers for boot location NOR/NAND */
292 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
293 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
294 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
295 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
296 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
297 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
298 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
299 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
300 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
301 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
302 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
303 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
304 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
305 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
306 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
308 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
309 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
310 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
311 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
312 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
313 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
314 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
315 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
316 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
317 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
318 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
319 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
320 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
321 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
325 #define CONFIG_SYS_CPLD_BASE 0xffb00000
327 #ifdef CONFIG_PHYS_64BIT
328 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
330 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
333 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
337 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
338 #define CONFIG_SYS_CSOR3 0x0
339 /* CPLD Timing parameters for IFC CS3 */
340 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
341 FTIM0_GPCM_TEADC(0x0e) | \
342 FTIM0_GPCM_TEAHC(0x0e))
343 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
344 FTIM1_GPCM_TRAD(0x1f))
345 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
346 FTIM2_GPCM_TCH(0x8) | \
347 FTIM2_GPCM_TWP(0x1f))
348 #define CONFIG_SYS_CS3_FTIM3 0x0
350 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
351 #define CONFIG_SYS_RAMBOOT
353 #undef CONFIG_SYS_RAMBOOT
356 #define CONFIG_SYS_INIT_RAM_LOCK
357 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
358 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
360 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
362 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
365 * Config the L2 Cache as L2 SRAM
367 #if defined(CONFIG_SPL_BUILD)
368 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
369 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
370 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
371 #define CONFIG_SYS_L2_SIZE (256 << 10)
372 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
373 #elif defined(CONFIG_MTD_RAW_NAND)
374 #ifdef CONFIG_TPL_BUILD
375 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
376 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
377 #define CONFIG_SYS_L2_SIZE (256 << 10)
378 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
380 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
381 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
382 #define CONFIG_SYS_L2_SIZE (256 << 10)
383 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
389 #undef CONFIG_SERIAL_SOFTWARE_FIFO
390 #define CONFIG_SYS_NS16550_SERIAL
391 #define CONFIG_SYS_NS16550_REG_SIZE 1
392 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
393 #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
394 #define CONFIG_NS16550_MIN_FUNCTIONS
397 #define CONFIG_SYS_BAUDRATE_TABLE \
398 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
400 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
401 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
404 #define I2C_PCA9557_ADDR1 0x18
405 #define I2C_PCA9557_ADDR2 0x19
406 #define I2C_PCA9557_BUS_NUM 0
409 #if defined(CONFIG_TARGET_P1010RDB_PB)
410 #ifdef CONFIG_ID_EEPROM
411 #define CONFIG_SYS_I2C_EEPROM_NXID
413 #define CONFIG_SYS_EEPROM_BUS_NUM 0
414 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
416 /* enable read and write access to EEPROM */
419 #define CONFIG_RTC_PT7C4338
420 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
423 * SPI interface will not be available in case of NAND boot SPI CS0 will be
426 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
427 /* eSPI - Enhanced SPI */
430 #if defined(CONFIG_TSEC_ENET)
431 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
432 #define CONFIG_TSEC1 1
433 #define CONFIG_TSEC1_NAME "eTSEC1"
434 #define CONFIG_TSEC2 1
435 #define CONFIG_TSEC2_NAME "eTSEC2"
436 #define CONFIG_TSEC3 1
437 #define CONFIG_TSEC3_NAME "eTSEC3"
439 #define TSEC1_PHY_ADDR 1
440 #define TSEC2_PHY_ADDR 0
441 #define TSEC3_PHY_ADDR 2
443 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
444 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
445 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
447 #define TSEC1_PHYIDX 0
448 #define TSEC2_PHYIDX 0
449 #define TSEC3_PHYIDX 0
451 /* TBI PHY configuration for SGMII mode */
452 #define CONFIG_TSEC_TBICR_SETTINGS ( \
454 | TBICR_ANEG_ENABLE \
455 | TBICR_FULL_DUPLEX \
459 #endif /* CONFIG_TSEC_ENET */
462 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
468 #if defined(CONFIG_MTD_RAW_NAND)
469 #ifdef CONFIG_TPL_BUILD
470 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
474 #define CONFIG_LOADS_ECHO /* echo on for serial download */
475 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
477 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
478 || defined(CONFIG_FSL_SATA)
482 * Miscellaneous configurable options
486 * For booting Linux, the board info and command line data
487 * have to be in the first 64 MB of memory, since this is
488 * the maximum mapped by the Linux kernel during initialization.
490 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
491 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
494 * Environment Configuration
497 #define CONFIG_ROOTPATH "/opt/nfsroot"
498 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
500 #define CONFIG_EXTRA_ENV_SETTINGS \
501 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
503 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
504 "loadaddr=1000000\0" \
505 "consoledev=ttyS0\0" \
506 "ramdiskaddr=2000000\0" \
507 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
508 "fdtaddr=1e00000\0" \
509 "fdtfile=p1010rdb.dtb\0" \
511 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
512 "othbootargs=ramdisk_size=600000\0" \
513 "usbfatboot=setenv bootargs root=/dev/ram rw " \
514 "console=$consoledev,$baudrate $othbootargs; " \
516 "fatload usb 0:2 $loadaddr $bootfile;" \
517 "fatload usb 0:2 $fdtaddr $fdtfile;" \
518 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
519 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
520 "usbext2boot=setenv bootargs root=/dev/ram rw " \
521 "console=$consoledev,$baudrate $othbootargs; " \
523 "ext2load usb 0:4 $loadaddr $bootfile;" \
524 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
525 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
526 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
529 #if defined(CONFIG_TARGET_P1010RDB_PA)
531 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
532 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
533 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
534 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
535 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
536 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
538 #elif defined(CONFIG_TARGET_P1010RDB_PB)
540 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
541 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
542 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
543 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
544 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
545 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
546 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
547 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
548 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
549 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
552 #include <asm/fsl_secure_boot.h>
554 #endif /* __CONFIG_H */