include/configs/P1010RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * P010 RDB board configuration file
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <asm/config_mpc85xx.h>
  14 #define CONFIG_NAND_FSL_IFC
  15
  16 #ifdef CONFIG_SDCARD
  17 #define CONFIG_SPL_FLUSH_IMAGE
  18 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  19 #define CONFIG_SPL_PAD_TO               0x18000
  20 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
  21 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  22 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  23 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  24 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  25 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  26 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  27 #ifdef CONFIG_SPL_BUILD
  28 #define CONFIG_SPL_COMMON_INIT_DDR
  29 #endif
  30 #endif
  31
  32 #ifdef CONFIG_SPIFLASH
  33 #ifdef CONFIG_SECURE_BOOT
  34 #define CONFIG_RAMBOOT_SPIFLASH
  35 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  36 #else
  37 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  38 #define CONFIG_SPL_FLUSH_IMAGE
  39 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  40 #define CONFIG_SPL_PAD_TO                       0x18000
  41 #define CONFIG_SPL_MAX_SIZE                     (96 * 1024)
  42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  46 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  47 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  48 #ifdef CONFIG_SPL_BUILD
  49 #define CONFIG_SPL_COMMON_INIT_DDR
  50 #endif
  51 #endif
  52 #endif
  53
  54 #ifdef CONFIG_NAND
  55 #ifdef CONFIG_SECURE_BOOT
  56 #define CONFIG_SPL_INIT_MINIMAL
  57 #define CONFIG_SPL_FLUSH_IMAGE
  58 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  59
  60 #define CONFIG_SPL_MAX_SIZE             8192
  61 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
  62 #define CONFIG_SPL_RELOC_STACK          0x00100000
  63 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
  64 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  65 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  66 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
  67 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  68 #else
  69 #ifdef CONFIG_TPL_BUILD
  70 #define CONFIG_SPL_FLUSH_IMAGE
  71 #define CONFIG_SPL_NAND_INIT
  72 #define CONFIG_SPL_COMMON_INIT_DDR
  73 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  74 #define CONFIG_TPL_TEXT_BASE            0xD0001000
  75 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  76 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
  77 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  78 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  79 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
  80 #elif defined(CONFIG_SPL_BUILD)
  81 #define CONFIG_SPL_INIT_MINIMAL
  82 #define CONFIG_SPL_NAND_MINIMAL
  83 #define CONFIG_SPL_FLUSH_IMAGE
  84 #define CONFIG_SPL_MAX_SIZE             8192
  85 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  86 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
  87 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
  88 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
  89 #endif
  90 #define CONFIG_SPL_PAD_TO       0x20000
  91 #define CONFIG_TPL_PAD_TO       0x20000
  92 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
  93 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  94 #endif
  95 #endif
  96
  97 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
  98 #define CONFIG_RAMBOOT_NAND
  99 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
 100 #endif
 101
 102 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 103 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 104 #endif
 105
 106 #ifdef CONFIG_TPL_BUILD
 107 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
 108 #elif defined(CONFIG_SPL_BUILD)
 109 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 110 #else
 111 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 112 #endif
 113
 114 /* High Level Configuration Options */
 115 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
 116
 117 #if defined(CONFIG_PCI)
 118 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 119 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
 120 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 121 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 122 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
 123 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 124
 125 /*
 126  * PCI Windows
 127  * Memory space is mapped 1-1, but I/O space must start from 0.
 128  */
 129 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 130 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe Slot"
 131 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 132 #ifdef CONFIG_PHYS_64BIT
 133 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 134 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 135 #else
 136 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 137 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 138 #endif
 139 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 140 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 141 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 142 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 143 #ifdef CONFIG_PHYS_64BIT
 144 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 145 #else
 146 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 147 #endif
 148
 149 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 150 #if defined(CONFIG_TARGET_P1010RDB_PA)
 151 #define CONFIG_SYS_PCIE2_NAME           "PCIe Slot"
 152 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 153 #define CONFIG_SYS_PCIE2_NAME           "mini PCIe Slot"
 154 #endif
 155 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 156 #ifdef CONFIG_PHYS_64BIT
 157 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 158 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 159 #else
 160 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 161 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 162 #endif
 163 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 164 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 165 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 166 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 167 #ifdef CONFIG_PHYS_64BIT
 168 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 169 #else
 170 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 171 #endif
 172
 173 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 174 #endif
 175
 176 #define CONFIG_ENV_OVERWRITE
 177
 178 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on P1010 RDB */
 179 #define CONFIG_SYS_CLK_FREQ     66666666 /* SYSCLK for P1010 RDB */
 180
 181 #define CONFIG_HWCONFIG
 182 /*
 183  * These can be toggled for performance analysis, otherwise use default.
 184  */
 185 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 186 #define CONFIG_BTB                      /* toggle branch predition */
 187
 188
 189 #define CONFIG_ENABLE_36BIT_PHYS
 190
 191 #ifdef CONFIG_PHYS_64BIT
 192 #define CONFIG_ADDR_MAP                 1
 193 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 194 #endif
 195
 196 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 197 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 198
 199 /* DDR Setup */
 200 #define CONFIG_SYS_DDR_RAW_TIMING
 201 #define CONFIG_DDR_SPD
 202 #define CONFIG_SYS_SPD_BUS_NUM          1
 203 #define SPD_EEPROM_ADDRESS              0x52
 204
 205 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 206
 207 #ifndef __ASSEMBLY__
 208 extern unsigned long get_sdram_size(void);
 209 #endif
 210 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 211 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 212 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 213
 214 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 215 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 216
 217 /* DDR3 Controller Settings */
 218 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 219 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 220 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 221 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 222 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 223 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 224 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 225 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 226 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 227 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 228 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 229 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
 230 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
 231 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 232 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 233
 234 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
 235 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
 236 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
 237 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
 238 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
 239 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
 240 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
 241 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
 242 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 243
 244 /* settings for DDR3 at 667MT/s */
 245 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
 246 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
 247 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
 248 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
 249 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
 250 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
 251 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
 252 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
 253 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
 254
 255 #define CONFIG_SYS_CCSRBAR                      0xffe00000
 256 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
 257
 258 /* Don't relocate CCSRBAR while in NAND_SPL */
 259 #ifdef CONFIG_SPL_BUILD
 260 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 261 #endif
 262
 263 /*
 264  * Memory map
 265  *
 266  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 267  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 268  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 269  *
 270  * Localbus non-cacheable
 271  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 272  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 273  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 274  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 275  */
 276
 277 /*
 278  * IFC Definitions
 279  */
 280 /* NOR Flash on IFC */
 281
 282 #define CONFIG_SYS_FLASH_BASE           0xee000000
 283 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 284
 285 #ifdef CONFIG_PHYS_64BIT
 286 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 287 #else
 288 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 289 #endif
 290
 291 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 292                                 CSPR_PORT_SIZE_16 | \
 293                                 CSPR_MSEL_NOR | \
 294                                 CSPR_V)
 295 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
 296 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
 297 /* NOR Flash Timing Params */
 298 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
 299                                 FTIM0_NOR_TEADC(0x5) | \
 300                                 FTIM0_NOR_TEAHC(0x5)
 301 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
 302                                 FTIM1_NOR_TRAD_NOR(0x0f)
 303 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
 304                                 FTIM2_NOR_TCH(0x4) | \
 305                                 FTIM2_NOR_TWP(0x1c)
 306 #define CONFIG_SYS_NOR_FTIM3    0x0
 307
 308 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 309 #define CONFIG_SYS_FLASH_QUIET_TEST
 310 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 311 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 312
 313 #undef CONFIG_SYS_FLASH_CHECKSUM
 314 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 315 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 316
 317 /* CFI for NOR Flash */
 318 #define CONFIG_SYS_FLASH_EMPTY_INFO
 319
 320 /* NAND Flash on IFC */
 321 #define CONFIG_SYS_NAND_BASE            0xff800000
 322 #ifdef CONFIG_PHYS_64BIT
 323 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 324 #else
 325 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 326 #endif
 327
 328 #define CONFIG_MTD_PARTITION
 329
 330 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 331                                 | CSPR_PORT_SIZE_8      \
 332                                 | CSPR_MSEL_NAND        \
 333                                 | CSPR_V)
 334 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 335
 336 #if defined(CONFIG_TARGET_P1010RDB_PA)
 337 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 338                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 339                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 340                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 341                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 342                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 343                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 344 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 345
 346 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 347 #define CONFIG_SYS_NAND_ONFI_DETECTION
 348 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 349                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 350                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 351                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 352                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 353                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 354                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 355 #define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
 356 #endif
 357
 358 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 359 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 360
 361 #if defined(CONFIG_TARGET_P1010RDB_PA)
 362 /* NAND Flash Timing Params */
 363 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
 364                                         FTIM0_NAND_TWP(0x0C)   | \
 365                                         FTIM0_NAND_TWCHT(0x04) | \
 366                                         FTIM0_NAND_TWH(0x05)
 367 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
 368                                         FTIM1_NAND_TWBE(0x1d)  | \
 369                                         FTIM1_NAND_TRR(0x07)   | \
 370                                         FTIM1_NAND_TRP(0x0c)
 371 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
 372                                         FTIM2_NAND_TREH(0x05) | \
 373                                         FTIM2_NAND_TWHRE(0x0f)
 374 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 375
 376 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 377 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 378 /* ONFI NAND Flash mode0 Timing Params */
 379 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 380                                         FTIM0_NAND_TWP(0x18)   | \
 381                                         FTIM0_NAND_TWCHT(0x07) | \
 382                                         FTIM0_NAND_TWH(0x0a))
 383 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 384                                         FTIM1_NAND_TWBE(0x39)  | \
 385                                         FTIM1_NAND_TRR(0x0e)   | \
 386                                         FTIM1_NAND_TRP(0x18))
 387 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 388                                         FTIM2_NAND_TREH(0x0a)  | \
 389                                         FTIM2_NAND_TWHRE(0x1e))
 390 #define CONFIG_SYS_NAND_FTIM3   0x0
 391 #endif
 392
 393 #define CONFIG_SYS_NAND_DDR_LAW         11
 394
 395 /* Set up IFC registers for boot location NOR/NAND */
 396 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
 397 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 398 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 399 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 400 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 401 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 402 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 403 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 404 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 405 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 406 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 407 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 408 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 409 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 410 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 411 #else
 412 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 413 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 414 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 415 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 416 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 417 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 418 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 419 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 420 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 421 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 422 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 423 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 424 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 425 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 426 #endif
 427
 428 /* CPLD on IFC */
 429 #define CONFIG_SYS_CPLD_BASE            0xffb00000
 430
 431 #ifdef CONFIG_PHYS_64BIT
 432 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
 433 #else
 434 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 435 #endif
 436
 437 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 438                                 | CSPR_PORT_SIZE_8 \
 439                                 | CSPR_MSEL_GPCM \
 440                                 | CSPR_V)
 441 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
 442 #define CONFIG_SYS_CSOR3                0x0
 443 /* CPLD Timing parameters for IFC CS3 */
 444 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 445                                         FTIM0_GPCM_TEADC(0x0e) | \
 446                                         FTIM0_GPCM_TEAHC(0x0e))
 447 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 448                                         FTIM1_GPCM_TRAD(0x1f))
 449 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 450                                         FTIM2_GPCM_TCH(0x8) | \
 451                                         FTIM2_GPCM_TWP(0x1f))
 452 #define CONFIG_SYS_CS3_FTIM3            0x0
 453
 454 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
 455         defined(CONFIG_RAMBOOT_NAND)
 456 #define CONFIG_SYS_RAMBOOT
 457 #else
 458 #undef CONFIG_SYS_RAMBOOT
 459 #endif
 460
 461 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 462 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
 463 #define CONFIG_A003399_NOR_WORKAROUND
 464 #endif
 465 #endif
 466
 467 #define CONFIG_SYS_INIT_RAM_LOCK
 468 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 469 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 470
 471 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 472                                                 - GENERATED_GBL_DATA_SIZE)
 473 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 474
 475 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 476 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 477
 478 /*
 479  * Config the L2 Cache as L2 SRAM
 480  */
 481 #if defined(CONFIG_SPL_BUILD)
 482 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 483 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 484 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 485 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 486 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 487 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 488 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 489 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 490 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (128 << 10)
 491 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
 492 #elif defined(CONFIG_NAND)
 493 #ifdef CONFIG_TPL_BUILD
 494 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 495 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 496 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 497 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 498 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 499 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 500 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 501 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 502 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 503 #else
 504 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 505 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 506 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 507 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 508 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
 509 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 510 #endif
 511 #endif
 512 #endif
 513
 514 /* Serial Port */
 515 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 516 #define CONFIG_SYS_NS16550_SERIAL
 517 #define CONFIG_SYS_NS16550_REG_SIZE     1
 518 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 519 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 520 #define CONFIG_NS16550_MIN_FUNCTIONS
 521 #endif
 522
 523 #define CONFIG_SYS_BAUDRATE_TABLE       \
 524         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 525
 526 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 527 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 528
 529 /* I2C */
 530 #define CONFIG_SYS_I2C
 531 #define CONFIG_SYS_I2C_FSL
 532 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 533 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 534 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 535 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 536 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 537 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 538 #define I2C_PCA9557_ADDR1               0x18
 539 #define I2C_PCA9557_ADDR2               0x19
 540 #define I2C_PCA9557_BUS_NUM             0
 541
 542 /* I2C EEPROM */
 543 #if defined(CONFIG_TARGET_P1010RDB_PB)
 544 #define CONFIG_ID_EEPROM
 545 #ifdef CONFIG_ID_EEPROM
 546 #define CONFIG_SYS_I2C_EEPROM_NXID
 547 #endif
 548 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 549 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 550 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 551 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 552 #endif
 553 /* enable read and write access to EEPROM */
 554 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 555 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 556 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 557
 558 /* RTC */
 559 #define CONFIG_RTC_PT7C4338
 560 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 561
 562 /*
 563  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 564  * used for SLIC
 565  */
 566 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
 567 /* eSPI - Enhanced SPI */
 568 #endif
 569
 570 #if defined(CONFIG_TSEC_ENET)
 571 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 572 #define CONFIG_TSEC1    1
 573 #define CONFIG_TSEC1_NAME       "eTSEC1"
 574 #define CONFIG_TSEC2    1
 575 #define CONFIG_TSEC2_NAME       "eTSEC2"
 576 #define CONFIG_TSEC3    1
 577 #define CONFIG_TSEC3_NAME       "eTSEC3"
 578
 579 #define TSEC1_PHY_ADDR          1
 580 #define TSEC2_PHY_ADDR          0
 581 #define TSEC3_PHY_ADDR          2
 582
 583 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 584 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 585 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 586
 587 #define TSEC1_PHYIDX            0
 588 #define TSEC2_PHYIDX            0
 589 #define TSEC3_PHYIDX            0
 590
 591 #define CONFIG_ETHPRIME         "eTSEC1"
 592
 593 /* TBI PHY configuration for SGMII mode */
 594 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 595                 TBICR_PHY_RESET \
 596                 | TBICR_ANEG_ENABLE \
 597                 | TBICR_FULL_DUPLEX \
 598                 | TBICR_SPEED1_SET \
 599                 )
 600
 601 #endif  /* CONFIG_TSEC_ENET */
 602
 603 /* SATA */
 604 #define CONFIG_FSL_SATA_V2
 605
 606 #ifdef CONFIG_FSL_SATA
 607 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 608 #define CONFIG_SATA1
 609 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 610 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 611 #define CONFIG_SATA2
 612 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 613 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 614
 615 #define CONFIG_LBA48
 616 #endif /* #ifdef CONFIG_FSL_SATA  */
 617
 618 #ifdef CONFIG_MMC
 619 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 620 #endif
 621
 622 #define CONFIG_HAS_FSL_DR_USB
 623
 624 #if defined(CONFIG_HAS_FSL_DR_USB)
 625 #ifdef CONFIG_USB_EHCI_HCD
 626 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 627 #define CONFIG_USB_EHCI_FSL
 628 #endif
 629 #endif
 630
 631 /*
 632  * Environment
 633  */
 634 #if defined(CONFIG_SDCARD)
 635 #define CONFIG_FSL_FIXED_MMC_LOCATION
 636 #define CONFIG_SYS_MMC_ENV_DEV          0
 637 #define CONFIG_ENV_SIZE                 0x2000
 638 #elif defined(CONFIG_SPIFLASH)
 639 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 640 #define CONFIG_ENV_SECT_SIZE    0x10000
 641 #define CONFIG_ENV_SIZE         0x2000
 642 #elif defined(CONFIG_NAND)
 643 #ifdef CONFIG_TPL_BUILD
 644 #define CONFIG_ENV_SIZE         0x2000
 645 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 646 #else
 647 #if defined(CONFIG_TARGET_P1010RDB_PA)
 648 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 649 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
 650 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 651 #define CONFIG_ENV_SIZE         (16 * 1024)
 652 #define CONFIG_ENV_RANGE        (32 * CONFIG_ENV_SIZE) /* new block size 512K */
 653 #endif
 654 #endif
 655 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 656 #elif defined(CONFIG_SYS_RAMBOOT)
 657 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - 0x1000)
 658 #define CONFIG_ENV_SIZE                 0x2000
 659 #else
 660 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 661 #define CONFIG_ENV_SIZE         0x2000
 662 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 663 #endif
 664
 665 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 666 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 667
 668 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 669
 670 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
 671                  || defined(CONFIG_FSL_SATA)
 672 #endif
 673
 674 /*
 675  * Miscellaneous configurable options
 676  */
 677 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 678
 679 /*
 680  * For booting Linux, the board info and command line data
 681  * have to be in the first 64 MB of memory, since this is
 682  * the maximum mapped by the Linux kernel during initialization.
 683  */
 684 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 685 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 686
 687 #if defined(CONFIG_CMD_KGDB)
 688 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 689 #endif
 690
 691 /*
 692  * Environment Configuration
 693  */
 694
 695 #if defined(CONFIG_TSEC_ENET)
 696 #define CONFIG_HAS_ETH0
 697 #define CONFIG_HAS_ETH1
 698 #define CONFIG_HAS_ETH2
 699 #endif
 700
 701 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 702 #define CONFIG_BOOTFILE         "uImage"
 703 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 704
 705 /* default location for tftp and bootm */
 706 #define CONFIG_LOADADDR         1000000
 707
 708 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 709         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 710         "netdev=eth0\0"                                         \
 711         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 712         "loadaddr=1000000\0"                    \
 713         "consoledev=ttyS0\0"                            \
 714         "ramdiskaddr=2000000\0"                 \
 715         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 716         "fdtaddr=1e00000\0"                             \
 717         "fdtfile=p1010rdb.dtb\0"                \
 718         "bdev=sda1\0"   \
 719         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 720         "othbootargs=ramdisk_size=600000\0" \
 721         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 722         "console=$consoledev,$baudrate $othbootargs; "  \
 723         "usb start;"                    \
 724         "fatload usb 0:2 $loadaddr $bootfile;"          \
 725         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 726         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 727         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 728         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 729         "console=$consoledev,$baudrate $othbootargs; "  \
 730         "usb start;"                    \
 731         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 732         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 733         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 734         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 735         CONFIG_BOOTMODE
 736
 737 #if defined(CONFIG_TARGET_P1010RDB_PA)
 738 #define CONFIG_BOOTMODE \
 739         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 740         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 741         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 742         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 743         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 744         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 745
 746 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 747 #define CONFIG_BOOTMODE \
 748         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 749         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 750         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 751         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 752         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 753         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 754         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 755         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 756         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 757         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 758 #endif
 759
 760 #define CONFIG_RAMBOOTCOMMAND           \
 761         "setenv bootargs root=/dev/ram rw "     \
 762         "console=$consoledev,$baudrate $othbootargs; "  \
 763         "tftp $ramdiskaddr $ramdiskfile;"       \
 764         "tftp $loadaddr $bootfile;"             \
 765         "tftp $fdtaddr $fdtfile;"               \
 766         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 767
 768 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 769
 770 #include <asm/fsl_secure_boot.h>
 771
 772 #endif  /* __CONFIG_H */