2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * P010 RDB board configuration file
31 #define CONFIG_PHYS_64BIT
34 #ifdef CONFIG_P1010RDB
36 #define CONFIG_NAND_FSL_IFC
40 #define CONFIG_RAMBOOT_SDCARD
41 #define CONFIG_SYS_TEXT_BASE 0x11000000
42 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
45 #ifdef CONFIG_SPIFLASH
46 #define CONFIG_RAMBOOT_SPIFLASH
47 #define CONFIG_SYS_TEXT_BASE 0x11000000
48 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
51 #ifdef CONFIG_NAND /* NAND Boot */
52 #define CONFIG_RAMBOOT_NAND
53 #define CONFIG_NAND_U_BOOT
54 #define CONFIG_SYS_TEXT_BASE_SPL 0xff800000
55 #ifdef CONFIG_NAND_SPL
56 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL
58 #define CONFIG_SYS_TEXT_BASE 0x11001000
59 #endif /* CONFIG_NAND_SPL */
63 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
64 #define CONFIG_RAMBOOT_NAND
65 #define CONFIG_SYS_TEXT_BASE 0x11000000
66 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
69 #ifndef CONFIG_SYS_TEXT_BASE
70 #define CONFIG_SYS_TEXT_BASE 0xeff80000
73 #ifndef CONFIG_RESET_VECTOR_ADDRESS
74 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
77 #ifndef CONFIG_SYS_MONITOR_BASE
78 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
81 /* High Level Configuration Options */
82 #define CONFIG_BOOKE /* BOOKE */
83 #define CONFIG_E500 /* BOOKE e500 family */
84 #define CONFIG_MPC85xx
85 #define CONFIG_FSL_IFC /* Enable IFC Support */
86 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
88 #define CONFIG_PCI /* Enable PCI/PCIE */
89 #if defined(CONFIG_PCI)
90 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
91 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
92 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
93 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
94 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
95 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
97 #define CONFIG_CMD_NET
98 #define CONFIG_CMD_PCI
100 #define CONFIG_E1000 /* E1000 pci Ethernet card*/
104 * Memory space is mapped 1-1, but I/O space must start from 0.
106 /* controller 1, Slot 1, tgtid 1, Base address a000 */
107 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
108 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
109 #ifdef CONFIG_PHYS_64BIT
110 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
111 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
113 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
114 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
116 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
117 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
118 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
119 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
120 #ifdef CONFIG_PHYS_64BIT
121 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
123 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
126 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
127 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
128 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
129 #ifdef CONFIG_PHYS_64BIT
130 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
131 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
133 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
134 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
136 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
137 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
138 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
139 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
140 #ifdef CONFIG_PHYS_64BIT
141 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
143 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
146 #define CONFIG_PCI_PNP /* do pci plug-and-play */
148 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
149 #define CONFIG_DOS_PARTITION
152 #define CONFIG_FSL_LAW /* Use common FSL init code */
153 #define CONFIG_TSEC_ENET
154 #define CONFIG_ENV_OVERWRITE
156 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
157 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
159 #ifndef CONFIG_SDCARD
160 #define CONFIG_MISC_INIT_R
163 #define CONFIG_HWCONFIG
165 * These can be toggled for performance analysis, otherwise use default.
167 #define CONFIG_L2_CACHE /* toggle L2 cache */
168 #define CONFIG_BTB /* toggle branch predition */
170 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
172 #define CONFIG_ENABLE_36BIT_PHYS
174 #ifdef CONFIG_PHYS_64BIT
175 #define CONFIG_ADDR_MAP 1
176 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
179 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
180 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
181 #define CONFIG_PANIC_HANG /* do not reset board on panic */
184 #define CONFIG_FSL_DDR3
185 #define CONFIG_SYS_DDR_RAW_TIMING
186 #define CONFIG_DDR_SPD
187 #define CONFIG_SYS_SPD_BUS_NUM 1
188 #define SPD_EEPROM_ADDRESS 0x52
190 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
193 extern unsigned long get_sdram_size(void);
195 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
196 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
197 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
199 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
200 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
202 /* DDR3 Controller Settings */
203 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
204 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
205 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
206 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
207 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
208 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
209 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
211 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
212 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
213 #define CONFIG_SYS_DDR_RCW_1 0x00000000
214 #define CONFIG_SYS_DDR_RCW_2 0x00000000
215 #define CONFIG_SYS_DDR_CONTROL 0x470C0000 /* Type = DDR3 */
216 #define CONFIG_SYS_DDR_CONTROL_2 0x04401010
217 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
218 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
220 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
221 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
222 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4644
223 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
224 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
225 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520
226 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
227 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
228 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
230 /* settings for DDR3 at 667MT/s */
231 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
232 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
233 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
234 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
235 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
236 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
237 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
238 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
239 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
241 #define CONFIG_SYS_CCSRBAR 0xffe00000
242 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
244 /* Don't relocate CCSRBAR while in NAND_SPL */
245 #ifdef CONFIG_NAND_SPL
246 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
252 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
253 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
254 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
256 * Localbus non-cacheable
257 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
258 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
259 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
260 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
263 /* In case of SD card boot, IFC interface is not available because of muxing */
265 #define CONFIG_SYS_NO_FLASH
270 /* NOR Flash on IFC */
271 #define CONFIG_SYS_FLASH_BASE 0xee000000
272 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
274 #ifdef CONFIG_PHYS_64BIT
275 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
277 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
280 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
281 CSPR_PORT_SIZE_16 | \
284 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
285 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
286 /* NOR Flash Timing Params */
287 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
288 FTIM0_NOR_TEADC(0x5) | \
290 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
291 FTIM1_NOR_TRAD_NOR(0x0f)
292 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
293 FTIM2_NOR_TCH(0x4) | \
295 #define CONFIG_SYS_NOR_FTIM3 0x0
297 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
298 #define CONFIG_SYS_FLASH_QUIET_TEST
299 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
300 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
302 #undef CONFIG_SYS_FLASH_CHECKSUM
303 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
304 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
306 /* CFI for NOR Flash */
307 #define CONFIG_FLASH_CFI_DRIVER
308 #define CONFIG_SYS_FLASH_CFI
309 #define CONFIG_SYS_FLASH_EMPTY_INFO
310 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
312 /* NAND Flash on IFC */
313 #define CONFIG_SYS_NAND_BASE 0xff800000
314 #ifdef CONFIG_PHYS_64BIT
315 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
317 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
320 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
324 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
325 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
326 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
327 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
328 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
329 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
330 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
331 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
333 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
334 #define CONFIG_SYS_MAX_NAND_DEVICE 1
335 #define CONFIG_MTD_NAND_VERIFY_WRITE
336 #define CONFIG_CMD_NAND
337 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
339 /* NAND Flash Timing Params */
340 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
341 FTIM0_NAND_TWP(0x0C) | \
342 FTIM0_NAND_TWCHT(0x04) | \
344 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
345 FTIM1_NAND_TWBE(0x1d) | \
346 FTIM1_NAND_TRR(0x07) | \
348 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
349 FTIM2_NAND_TREH(0x05) | \
350 FTIM2_NAND_TWHRE(0x0f)
351 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
353 #define CONFIG_SYS_NAND_DDR_LAW 11
355 /* Set up IFC registers for boot location NOR/NAND */
356 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SECBOOT)
357 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
358 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
359 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
360 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
361 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
362 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
363 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
364 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
365 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
366 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
367 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
368 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
369 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
370 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
372 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
373 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
374 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
375 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
376 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
377 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
378 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
379 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
380 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
381 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
382 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
383 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
384 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
385 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
388 /* NAND boot: 8K NAND loader config */
389 #define CONFIG_SYS_NAND_SPL_SIZE 0x2000
390 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
391 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
392 #define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
393 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
394 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x10000
395 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
398 #define CONFIG_SYS_CPLD_BASE 0xffb00000
400 #ifdef CONFIG_PHYS_64BIT
401 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
403 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
406 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
410 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
411 #define CONFIG_SYS_CSOR3 0x0
412 /* CPLD Timing parameters for IFC CS3 */
413 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
414 FTIM0_GPCM_TEADC(0x0e) | \
415 FTIM0_GPCM_TEAHC(0x0e))
416 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
417 FTIM1_GPCM_TRAD(0x1f))
418 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
419 FTIM2_GPCM_TCH(0x0) | \
420 FTIM2_GPCM_TWP(0x1f))
421 #define CONFIG_SYS_CS3_FTIM3 0x0
422 #endif /* CONFIG_SDCARD */
424 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
425 defined(CONFIG_RAMBOOT_NAND)
426 #define CONFIG_SYS_RAMBOOT
427 #define CONFIG_SYS_EXTRA_ENV_RELOC
429 #undef CONFIG_SYS_RAMBOOT
432 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
433 #define CONFIG_BOARD_EARLY_INIT_R
435 #define CONFIG_SYS_INIT_RAM_LOCK
436 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
437 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
439 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
440 - GENERATED_GBL_DATA_SIZE)
441 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
443 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
444 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
447 #define CONFIG_CONS_INDEX 1
448 #undef CONFIG_SERIAL_SOFTWARE_FIFO
449 #define CONFIG_SYS_NS16550
450 #define CONFIG_SYS_NS16550_SERIAL
451 #define CONFIG_SYS_NS16550_REG_SIZE 1
452 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
453 #ifdef CONFIG_NAND_SPL
454 #define CONFIG_NS16550_MIN_FUNCTIONS
457 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
459 #define CONFIG_SYS_BAUDRATE_TABLE \
460 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
462 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
463 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
465 /* Use the HUSH parser */
466 #define CONFIG_SYS_HUSH_PARSER
469 * Pass open firmware flat tree
471 #define CONFIG_OF_LIBFDT
472 #define CONFIG_OF_BOARD_SETUP
473 #define CONFIG_OF_STDOUT_VIA_ALIAS
475 /* new uImage format support */
477 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
479 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
480 #define CONFIG_HARD_I2C /* I2C with hardware support */
481 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
482 #define CONFIG_I2C_MULTI_BUS
483 #define CONFIG_I2C_CMD_TREE
484 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
485 #define CONFIG_SYS_I2C_SLAVE 0x7F
486 #define CONFIG_SYS_I2C_OFFSET 0x3000
487 #define CONFIG_SYS_I2C2_OFFSET 0x3100
490 #undef CONFIG_ID_EEPROM
491 /* enable read and write access to EEPROM */
492 #define CONFIG_CMD_EEPROM
493 #define CONFIG_SYS_I2C_MULTI_EEPROMS
494 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
495 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
496 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
499 #define CONFIG_RTC_PT7C4338
500 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
502 #define CONFIG_CMD_I2C
505 * SPI interface will not be available in case of NAND boot SPI CS0 will be
508 #if !defined(CONFIG_NAND_U_BOOT) || !defined(CONFIG_NAND_SECBOOT)
509 /* eSPI - Enhanced SPI */
510 #define CONFIG_FSL_ESPI
511 #define CONFIG_SPI_FLASH
512 #define CONFIG_SPI_FLASH_SPANSION
513 #define CONFIG_CMD_SF
514 #define CONFIG_SF_DEFAULT_SPEED 10000000
515 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
518 #if defined(CONFIG_TSEC_ENET)
519 #define CONFIG_MII /* MII PHY management */
520 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
521 #define CONFIG_TSEC1 1
522 #define CONFIG_TSEC1_NAME "eTSEC1"
523 #define CONFIG_TSEC2 1
524 #define CONFIG_TSEC2_NAME "eTSEC2"
525 #define CONFIG_TSEC3 1
526 #define CONFIG_TSEC3_NAME "eTSEC3"
528 #define TSEC1_PHY_ADDR 1
529 #define TSEC2_PHY_ADDR 0
530 #define TSEC3_PHY_ADDR 2
532 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
533 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
534 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
536 #define TSEC1_PHYIDX 0
537 #define TSEC2_PHYIDX 0
538 #define TSEC3_PHYIDX 0
540 #define CONFIG_ETHPRIME "eTSEC1"
542 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
544 /* TBI PHY configuration for SGMII mode */
545 #define CONFIG_TSEC_TBICR_SETTINGS ( \
547 | TBICR_ANEG_ENABLE \
548 | TBICR_FULL_DUPLEX \
552 #endif /* CONFIG_TSEC_ENET */
556 #define CONFIG_FSL_SATA
557 #define CONFIG_FSL_SATA_V2
558 #define CONFIG_LIBATA
560 #ifdef CONFIG_FSL_SATA
561 #define CONFIG_SYS_SATA_MAX_DEVICE 2
563 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
564 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
566 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
567 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
569 #define CONFIG_CMD_SATA
571 #endif /* #ifdef CONFIG_FSL_SATA */
573 /* SD interface will only be available in case of SD boot */
576 #define CONFIG_DEF_HWCONFIG esdhc
580 #define CONFIG_CMD_MMC
581 #define CONFIG_DOS_PARTITION
582 #define CONFIG_FSL_ESDHC
583 #define CONFIG_GENERIC_MMC
584 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
587 #define CONFIG_HAS_FSL_DR_USB
589 #if defined(CONFIG_HAS_FSL_DR_USB)
590 #define CONFIG_USB_EHCI
592 #ifdef CONFIG_USB_EHCI
593 #define CONFIG_CMD_USB
594 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
595 #define CONFIG_USB_EHCI_FSL
596 #define CONFIG_USB_STORAGE
603 #if defined(CONFIG_SYS_RAMBOOT)
604 #if defined(CONFIG_RAMBOOT_SDCARD)
605 #define CONFIG_ENV_IS_IN_MMC
606 #define CONFIG_FSL_FIXED_MMC_LOCATION
607 #define CONFIG_SYS_MMC_ENV_DEV 0
608 #define CONFIG_ENV_SIZE 0x2000
609 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
610 #define CONFIG_ENV_IS_IN_SPI_FLASH
611 #define CONFIG_ENV_SPI_BUS 0
612 #define CONFIG_ENV_SPI_CS 0
613 #define CONFIG_ENV_SPI_MAX_HZ 10000000
614 #define CONFIG_ENV_SPI_MODE 0
615 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
616 #define CONFIG_ENV_SECT_SIZE 0x10000
617 #define CONFIG_ENV_SIZE 0x2000
618 #elif defined(CONFIG_NAND_U_BOOT)
619 #define CONFIG_ENV_IS_IN_NAND
620 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
621 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_U_BOOT_SIZE
622 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
624 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
625 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
626 #define CONFIG_ENV_SIZE 0x2000
629 #define CONFIG_ENV_IS_IN_FLASH
630 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
631 #define CONFIG_ENV_ADDR 0xfff80000
633 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
635 #define CONFIG_ENV_SIZE 0x2000
636 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
639 #define CONFIG_LOADS_ECHO /* echo on for serial download */
640 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
643 * Command line configuration.
645 #include <config_cmd_default.h>
647 #define CONFIG_CMD_DATE
648 #define CONFIG_CMD_ERRATA
649 #define CONFIG_CMD_ELF
650 #define CONFIG_CMD_IRQ
651 #define CONFIG_CMD_MII
652 #define CONFIG_CMD_PING
653 #define CONFIG_CMD_SETEXPR
654 #define CONFIG_CMD_REGINFO
656 #undef CONFIG_WATCHDOG /* watchdog disabled */
658 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
659 || defined(CONFIG_FSL_SATA)
660 #define CONFIG_CMD_EXT2
661 #define CONFIG_CMD_FAT
662 #define CONFIG_DOS_PARTITION
666 * Miscellaneous configurable options
668 #define CONFIG_SYS_LONGHELP /* undef to save memory */
669 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
670 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
671 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
672 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
674 #if defined(CONFIG_CMD_KGDB)
675 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
677 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
679 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
680 /* Print Buffer Size */
681 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
682 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
683 #define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */
686 * Internal Definitions
690 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
691 #define BOOTFLAG_WARM 0x02 /* Software reboot */
694 * For booting Linux, the board info and command line data
695 * have to be in the first 64 MB of memory, since this is
696 * the maximum mapped by the Linux kernel during initialization.
698 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
699 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
701 #if defined(CONFIG_CMD_KGDB)
702 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
703 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
707 * Environment Configuration
710 #if defined(CONFIG_TSEC_ENET)
711 #define CONFIG_HAS_ETH0
712 #define CONFIG_HAS_ETH1
713 #define CONFIG_HAS_ETH2
716 #define CONFIG_HOSTNAME P1010RDB
717 #define CONFIG_ROOTPATH "/opt/nfsroot"
718 #define CONFIG_BOOTFILE "uImage"
719 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
721 /* default location for tftp and bootm */
722 #define CONFIG_LOADADDR 1000000
724 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
725 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
727 #define CONFIG_BAUDRATE 115200
729 #define CONFIG_EXTRA_ENV_SETTINGS \
730 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
732 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
733 "loadaddr=1000000\0" \
734 "consoledev=ttyS0\0" \
735 "ramdiskaddr=2000000\0" \
736 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
738 "fdtfile=p1010rdb.dtb\0" \
740 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
741 "othbootargs=ramdisk_size=600000\0" \
742 "usbfatboot=setenv bootargs root=/dev/ram rw " \
743 "console=$consoledev,$baudrate $othbootargs; " \
745 "fatload usb 0:2 $loadaddr $bootfile;" \
746 "fatload usb 0:2 $fdtaddr $fdtfile;" \
747 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
748 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
749 "usbext2boot=setenv bootargs root=/dev/ram rw " \
750 "console=$consoledev,$baudrate $othbootargs; " \
752 "ext2load usb 0:4 $loadaddr $bootfile;" \
753 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
754 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
755 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
757 #define CONFIG_RAMBOOTCOMMAND \
758 "setenv bootargs root=/dev/ram rw " \
759 "console=$consoledev,$baudrate $othbootargs; " \
760 "tftp $ramdiskaddr $ramdiskfile;" \
761 "tftp $loadaddr $bootfile;" \
762 "tftp $fdtaddr $fdtfile;" \
763 "bootm $loadaddr $ramdiskaddr $fdtaddr"
765 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
767 #ifdef CONFIG_SECURE_BOOT
768 #include <asm/fsl_secure_boot.h>
771 #endif /* __CONFIG_H */