1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * P010 RDB board configuration file
14 #include <linux/stringify.h>
16 #include <asm/config_mpc85xx.h>
19 #define CONFIG_SPL_FLUSH_IMAGE
20 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
21 #define CONFIG_SPL_PAD_TO 0x18000
22 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
23 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
24 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
25 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
26 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
27 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
28 #ifdef CONFIG_SPL_BUILD
29 #define CONFIG_SPL_COMMON_INIT_DDR
33 #ifdef CONFIG_SPIFLASH
34 #ifdef CONFIG_NXP_ESBC
35 #define CONFIG_RAMBOOT_SPIFLASH
36 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
38 #define CONFIG_SPL_SPI_FLASH_MINIMAL
39 #define CONFIG_SPL_FLUSH_IMAGE
40 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
41 #define CONFIG_SPL_PAD_TO 0x18000
42 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
47 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
48 #ifdef CONFIG_SPL_BUILD
49 #define CONFIG_SPL_COMMON_INIT_DDR
54 #ifdef CONFIG_MTD_RAW_NAND
55 #ifdef CONFIG_NXP_ESBC
56 #define CONFIG_SPL_INIT_MINIMAL
57 #define CONFIG_SPL_FLUSH_IMAGE
58 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
60 #define CONFIG_SPL_MAX_SIZE 8192
61 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
62 #define CONFIG_SPL_RELOC_STACK 0x00100000
63 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
64 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
65 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
67 #ifdef CONFIG_TPL_BUILD
68 #define CONFIG_SPL_FLUSH_IMAGE
69 #define CONFIG_SPL_NAND_INIT
70 #define CONFIG_SPL_COMMON_INIT_DDR
71 #define CONFIG_SPL_MAX_SIZE (128 << 10)
72 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
73 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
74 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
75 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
76 #elif defined(CONFIG_SPL_BUILD)
77 #define CONFIG_SPL_INIT_MINIMAL
78 #define CONFIG_SPL_NAND_MINIMAL
79 #define CONFIG_SPL_FLUSH_IMAGE
80 #define CONFIG_SPL_MAX_SIZE 8192
81 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
82 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
83 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
85 #define CONFIG_SPL_PAD_TO 0x20000
86 #define CONFIG_TPL_PAD_TO 0x20000
87 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
91 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
92 #define CONFIG_RAMBOOT_NAND
93 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
96 #ifndef CONFIG_RESET_VECTOR_ADDRESS
97 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
100 #ifdef CONFIG_TPL_BUILD
101 #define CONFIG_SYS_MONITOR_BASE 0xD0001000
102 #elif defined(CONFIG_SPL_BUILD)
103 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
105 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
108 /* High Level Configuration Options */
110 #if defined(CONFIG_PCI)
111 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
112 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
116 * Memory space is mapped 1-1, but I/O space must start from 0.
118 /* controller 1, Slot 1, tgtid 1, Base address a000 */
119 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
120 #ifdef CONFIG_PHYS_64BIT
121 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
123 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
125 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
126 #ifdef CONFIG_PHYS_64BIT
127 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
129 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
132 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
133 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
134 #ifdef CONFIG_PHYS_64BIT
135 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
137 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
139 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
140 #ifdef CONFIG_PHYS_64BIT
141 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
143 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
146 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
149 #define CONFIG_HWCONFIG
151 * These can be toggled for performance analysis, otherwise use default.
153 #define CONFIG_L2_CACHE /* toggle L2 cache */
156 #define CONFIG_ENABLE_36BIT_PHYS
159 #define CONFIG_SYS_DDR_RAW_TIMING
160 #define CONFIG_SYS_SPD_BUS_NUM 1
161 #define SPD_EEPROM_ADDRESS 0x52
163 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
166 extern unsigned long get_sdram_size(void);
168 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
169 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
170 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
172 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
174 /* DDR3 Controller Settings */
175 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
176 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
177 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
178 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
179 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
180 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
181 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
182 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
183 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
184 #define CONFIG_SYS_DDR_RCW_1 0x00000000
185 #define CONFIG_SYS_DDR_RCW_2 0x00000000
186 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
187 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
188 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
189 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
191 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
192 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
193 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
194 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
195 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
196 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
197 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
198 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
199 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
201 /* settings for DDR3 at 667MT/s */
202 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
203 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
204 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
205 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
206 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
207 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
208 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
209 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
210 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
212 #define CONFIG_SYS_CCSRBAR 0xffe00000
213 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
215 /* Don't relocate CCSRBAR while in NAND_SPL */
216 #ifdef CONFIG_SPL_BUILD
217 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
223 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
224 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
225 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
227 * Localbus non-cacheable
228 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
229 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
230 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
231 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
237 /* NOR Flash on IFC */
239 #define CONFIG_SYS_FLASH_BASE 0xee000000
240 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
242 #ifdef CONFIG_PHYS_64BIT
243 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
245 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
248 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
249 CSPR_PORT_SIZE_16 | \
252 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
253 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
254 /* NOR Flash Timing Params */
255 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
256 FTIM0_NOR_TEADC(0x5) | \
258 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
259 FTIM1_NOR_TRAD_NOR(0x0f)
260 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
261 FTIM2_NOR_TCH(0x4) | \
263 #define CONFIG_SYS_NOR_FTIM3 0x0
265 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
266 #define CONFIG_SYS_FLASH_QUIET_TEST
267 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
269 #undef CONFIG_SYS_FLASH_CHECKSUM
270 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
271 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
273 /* CFI for NOR Flash */
274 #define CONFIG_SYS_FLASH_EMPTY_INFO
276 /* NAND Flash on IFC */
277 #define CONFIG_SYS_NAND_BASE 0xff800000
278 #ifdef CONFIG_PHYS_64BIT
279 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
281 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
284 #define CONFIG_MTD_PARTITION
286 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
290 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
292 #if defined(CONFIG_TARGET_P1010RDB_PA)
293 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
294 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
295 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
296 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
297 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
298 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
299 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
301 #elif defined(CONFIG_TARGET_P1010RDB_PB)
302 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
303 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
304 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
305 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
306 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
307 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
308 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
311 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
312 #define CONFIG_SYS_MAX_NAND_DEVICE 1
314 #if defined(CONFIG_TARGET_P1010RDB_PA)
315 /* NAND Flash Timing Params */
316 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
317 FTIM0_NAND_TWP(0x0C) | \
318 FTIM0_NAND_TWCHT(0x04) | \
320 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
321 FTIM1_NAND_TWBE(0x1d) | \
322 FTIM1_NAND_TRR(0x07) | \
324 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
325 FTIM2_NAND_TREH(0x05) | \
326 FTIM2_NAND_TWHRE(0x0f)
327 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
329 #elif defined(CONFIG_TARGET_P1010RDB_PB)
330 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
331 /* ONFI NAND Flash mode0 Timing Params */
332 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
333 FTIM0_NAND_TWP(0x18) | \
334 FTIM0_NAND_TWCHT(0x07) | \
335 FTIM0_NAND_TWH(0x0a))
336 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
337 FTIM1_NAND_TWBE(0x39) | \
338 FTIM1_NAND_TRR(0x0e) | \
339 FTIM1_NAND_TRP(0x18))
340 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
341 FTIM2_NAND_TREH(0x0a) | \
342 FTIM2_NAND_TWHRE(0x1e))
343 #define CONFIG_SYS_NAND_FTIM3 0x0
346 #define CONFIG_SYS_NAND_DDR_LAW 11
348 /* Set up IFC registers for boot location NOR/NAND */
349 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
350 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
351 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
352 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
353 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
354 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
355 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
356 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
357 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
358 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
359 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
360 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
361 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
362 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
363 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
365 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
366 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
367 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
368 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
369 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
370 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
371 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
372 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
373 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
374 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
375 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
376 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
377 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
378 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
382 #define CONFIG_SYS_CPLD_BASE 0xffb00000
384 #ifdef CONFIG_PHYS_64BIT
385 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
387 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
390 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
394 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
395 #define CONFIG_SYS_CSOR3 0x0
396 /* CPLD Timing parameters for IFC CS3 */
397 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
398 FTIM0_GPCM_TEADC(0x0e) | \
399 FTIM0_GPCM_TEAHC(0x0e))
400 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
401 FTIM1_GPCM_TRAD(0x1f))
402 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
403 FTIM2_GPCM_TCH(0x8) | \
404 FTIM2_GPCM_TWP(0x1f))
405 #define CONFIG_SYS_CS3_FTIM3 0x0
407 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
408 defined(CONFIG_RAMBOOT_NAND)
409 #define CONFIG_SYS_RAMBOOT
411 #undef CONFIG_SYS_RAMBOOT
414 #define CONFIG_SYS_INIT_RAM_LOCK
415 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
416 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
418 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
419 - GENERATED_GBL_DATA_SIZE)
420 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
422 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
425 * Config the L2 Cache as L2 SRAM
427 #if defined(CONFIG_SPL_BUILD)
428 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
429 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
430 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
431 #define CONFIG_SYS_L2_SIZE (256 << 10)
432 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
433 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
434 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
435 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
436 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
437 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
438 #elif defined(CONFIG_MTD_RAW_NAND)
439 #ifdef CONFIG_TPL_BUILD
440 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
441 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
442 #define CONFIG_SYS_L2_SIZE (256 << 10)
443 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
444 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
445 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
446 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
447 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
448 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
450 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
451 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
452 #define CONFIG_SYS_L2_SIZE (256 << 10)
453 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
454 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
455 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
461 #undef CONFIG_SERIAL_SOFTWARE_FIFO
462 #define CONFIG_SYS_NS16550_SERIAL
463 #define CONFIG_SYS_NS16550_REG_SIZE 1
464 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
465 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
466 #define CONFIG_NS16550_MIN_FUNCTIONS
469 #define CONFIG_SYS_BAUDRATE_TABLE \
470 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
472 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
473 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
476 #define I2C_PCA9557_ADDR1 0x18
477 #define I2C_PCA9557_ADDR2 0x19
478 #define I2C_PCA9557_BUS_NUM 0
481 #if defined(CONFIG_TARGET_P1010RDB_PB)
482 #ifdef CONFIG_ID_EEPROM
483 #define CONFIG_SYS_I2C_EEPROM_NXID
485 #define CONFIG_SYS_EEPROM_BUS_NUM 0
486 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
488 /* enable read and write access to EEPROM */
491 #define CONFIG_RTC_PT7C4338
492 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
495 * SPI interface will not be available in case of NAND boot SPI CS0 will be
498 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
499 /* eSPI - Enhanced SPI */
502 #if defined(CONFIG_TSEC_ENET)
503 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
504 #define CONFIG_TSEC1 1
505 #define CONFIG_TSEC1_NAME "eTSEC1"
506 #define CONFIG_TSEC2 1
507 #define CONFIG_TSEC2_NAME "eTSEC2"
508 #define CONFIG_TSEC3 1
509 #define CONFIG_TSEC3_NAME "eTSEC3"
511 #define TSEC1_PHY_ADDR 1
512 #define TSEC2_PHY_ADDR 0
513 #define TSEC3_PHY_ADDR 2
515 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
516 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
517 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
519 #define TSEC1_PHYIDX 0
520 #define TSEC2_PHYIDX 0
521 #define TSEC3_PHYIDX 0
523 /* TBI PHY configuration for SGMII mode */
524 #define CONFIG_TSEC_TBICR_SETTINGS ( \
526 | TBICR_ANEG_ENABLE \
527 | TBICR_FULL_DUPLEX \
531 #endif /* CONFIG_TSEC_ENET */
534 #define CONFIG_FSL_SATA_V2
536 #ifdef CONFIG_FSL_SATA
538 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
539 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
541 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
542 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
545 #endif /* #ifdef CONFIG_FSL_SATA */
548 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
551 #define CONFIG_HAS_FSL_DR_USB
553 #if defined(CONFIG_HAS_FSL_DR_USB)
554 #ifdef CONFIG_USB_EHCI_HCD
555 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
562 #if defined(CONFIG_SDCARD)
563 #define CONFIG_FSL_FIXED_MMC_LOCATION
564 #elif defined(CONFIG_MTD_RAW_NAND)
565 #ifdef CONFIG_TPL_BUILD
566 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
568 #if defined(CONFIG_TARGET_P1010RDB_PA)
569 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
570 #elif defined(CONFIG_TARGET_P1010RDB_PB)
571 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
576 #define CONFIG_LOADS_ECHO /* echo on for serial download */
577 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
579 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
580 || defined(CONFIG_FSL_SATA)
584 * Miscellaneous configurable options
588 * For booting Linux, the board info and command line data
589 * have to be in the first 64 MB of memory, since this is
590 * the maximum mapped by the Linux kernel during initialization.
592 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
593 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
596 * Environment Configuration
599 #define CONFIG_ROOTPATH "/opt/nfsroot"
600 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
602 #define CONFIG_EXTRA_ENV_SETTINGS \
603 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
605 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
606 "loadaddr=1000000\0" \
607 "consoledev=ttyS0\0" \
608 "ramdiskaddr=2000000\0" \
609 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
610 "fdtaddr=1e00000\0" \
611 "fdtfile=p1010rdb.dtb\0" \
613 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
614 "othbootargs=ramdisk_size=600000\0" \
615 "usbfatboot=setenv bootargs root=/dev/ram rw " \
616 "console=$consoledev,$baudrate $othbootargs; " \
618 "fatload usb 0:2 $loadaddr $bootfile;" \
619 "fatload usb 0:2 $fdtaddr $fdtfile;" \
620 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
621 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
622 "usbext2boot=setenv bootargs root=/dev/ram rw " \
623 "console=$consoledev,$baudrate $othbootargs; " \
625 "ext2load usb 0:4 $loadaddr $bootfile;" \
626 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
627 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
628 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
631 #if defined(CONFIG_TARGET_P1010RDB_PA)
633 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
634 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
635 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
636 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
637 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
638 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
640 #elif defined(CONFIG_TARGET_P1010RDB_PB)
642 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
643 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
644 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
645 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
646 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
647 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
648 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
649 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
650 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
651 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
654 #include <asm/fsl_secure_boot.h>
656 #endif /* __CONFIG_H */