1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * P010 RDB board configuration file
14 #include <linux/stringify.h>
16 #include <asm/config_mpc85xx.h>
19 #define CONFIG_SPL_FLUSH_IMAGE
20 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
21 #define CONFIG_SPL_PAD_TO 0x18000
22 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
23 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
24 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
25 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
26 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
27 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
28 #ifdef CONFIG_SPL_BUILD
29 #define CONFIG_SPL_COMMON_INIT_DDR
33 #ifdef CONFIG_SPIFLASH
34 #ifdef CONFIG_NXP_ESBC
35 #define CONFIG_RAMBOOT_SPIFLASH
36 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
38 #define CONFIG_SPL_SPI_FLASH_MINIMAL
39 #define CONFIG_SPL_FLUSH_IMAGE
40 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
41 #define CONFIG_SPL_PAD_TO 0x18000
42 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
47 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
48 #ifdef CONFIG_SPL_BUILD
49 #define CONFIG_SPL_COMMON_INIT_DDR
54 #ifdef CONFIG_MTD_RAW_NAND
55 #ifdef CONFIG_NXP_ESBC
56 #define CONFIG_SPL_INIT_MINIMAL
57 #define CONFIG_SPL_FLUSH_IMAGE
58 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
60 #define CONFIG_SPL_MAX_SIZE 8192
61 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
62 #define CONFIG_SPL_RELOC_STACK 0x00100000
63 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
64 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
65 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
67 #ifdef CONFIG_TPL_BUILD
68 #define CONFIG_SPL_FLUSH_IMAGE
69 #define CONFIG_SPL_NAND_INIT
70 #define CONFIG_SPL_COMMON_INIT_DDR
71 #define CONFIG_SPL_MAX_SIZE (128 << 10)
72 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
73 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
74 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
75 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
76 #elif defined(CONFIG_SPL_BUILD)
77 #define CONFIG_SPL_INIT_MINIMAL
78 #define CONFIG_SPL_NAND_MINIMAL
79 #define CONFIG_SPL_FLUSH_IMAGE
80 #define CONFIG_SPL_MAX_SIZE 8192
81 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
82 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
83 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
85 #define CONFIG_SPL_PAD_TO 0x20000
86 #define CONFIG_TPL_PAD_TO 0x20000
87 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
91 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
92 #define CONFIG_RAMBOOT_NAND
93 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
96 #ifndef CONFIG_RESET_VECTOR_ADDRESS
97 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
100 #ifdef CONFIG_TPL_BUILD
101 #define CONFIG_SYS_MONITOR_BASE 0xD0001000
102 #elif defined(CONFIG_SPL_BUILD)
103 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
105 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
108 /* High Level Configuration Options */
110 #if defined(CONFIG_PCI)
111 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
112 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
116 * Memory space is mapped 1-1, but I/O space must start from 0.
118 /* controller 1, Slot 1, tgtid 1, Base address a000 */
119 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
120 #ifdef CONFIG_PHYS_64BIT
121 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
123 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
125 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
126 #ifdef CONFIG_PHYS_64BIT
127 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
129 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
132 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
133 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
134 #ifdef CONFIG_PHYS_64BIT
135 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
137 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
139 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
140 #ifdef CONFIG_PHYS_64BIT
141 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
143 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
146 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
149 #define CONFIG_HWCONFIG
151 * These can be toggled for performance analysis, otherwise use default.
153 #define CONFIG_L2_CACHE /* toggle L2 cache */
154 #define CONFIG_BTB /* toggle branch predition */
157 #define CONFIG_ENABLE_36BIT_PHYS
160 #define CONFIG_SYS_DDR_RAW_TIMING
161 #define CONFIG_SYS_SPD_BUS_NUM 1
162 #define SPD_EEPROM_ADDRESS 0x52
164 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
167 extern unsigned long get_sdram_size(void);
169 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
170 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
171 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
173 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
174 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
176 /* DDR3 Controller Settings */
177 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
178 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
179 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
180 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
181 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
182 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
183 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
184 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
185 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
186 #define CONFIG_SYS_DDR_RCW_1 0x00000000
187 #define CONFIG_SYS_DDR_RCW_2 0x00000000
188 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
189 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
190 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
191 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
193 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
194 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
195 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
196 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
197 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
198 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
199 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
200 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
201 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
203 /* settings for DDR3 at 667MT/s */
204 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
205 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
206 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
207 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
208 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
209 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
210 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
211 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
212 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
214 #define CONFIG_SYS_CCSRBAR 0xffe00000
215 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
217 /* Don't relocate CCSRBAR while in NAND_SPL */
218 #ifdef CONFIG_SPL_BUILD
219 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
225 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
226 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
227 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
229 * Localbus non-cacheable
230 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
231 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
232 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
233 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
239 /* NOR Flash on IFC */
241 #define CONFIG_SYS_FLASH_BASE 0xee000000
242 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
244 #ifdef CONFIG_PHYS_64BIT
245 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
247 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
250 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
251 CSPR_PORT_SIZE_16 | \
254 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
255 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
256 /* NOR Flash Timing Params */
257 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
258 FTIM0_NOR_TEADC(0x5) | \
260 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
261 FTIM1_NOR_TRAD_NOR(0x0f)
262 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
263 FTIM2_NOR_TCH(0x4) | \
265 #define CONFIG_SYS_NOR_FTIM3 0x0
267 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
268 #define CONFIG_SYS_FLASH_QUIET_TEST
269 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
271 #undef CONFIG_SYS_FLASH_CHECKSUM
272 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
273 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
275 /* CFI for NOR Flash */
276 #define CONFIG_SYS_FLASH_EMPTY_INFO
278 /* NAND Flash on IFC */
279 #define CONFIG_SYS_NAND_BASE 0xff800000
280 #ifdef CONFIG_PHYS_64BIT
281 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
283 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
286 #define CONFIG_MTD_PARTITION
288 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
292 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
294 #if defined(CONFIG_TARGET_P1010RDB_PA)
295 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
296 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
297 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
298 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
299 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
300 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
301 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
303 #elif defined(CONFIG_TARGET_P1010RDB_PB)
304 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
305 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
306 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
307 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
308 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
309 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
310 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
313 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
314 #define CONFIG_SYS_MAX_NAND_DEVICE 1
316 #if defined(CONFIG_TARGET_P1010RDB_PA)
317 /* NAND Flash Timing Params */
318 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
319 FTIM0_NAND_TWP(0x0C) | \
320 FTIM0_NAND_TWCHT(0x04) | \
322 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
323 FTIM1_NAND_TWBE(0x1d) | \
324 FTIM1_NAND_TRR(0x07) | \
326 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
327 FTIM2_NAND_TREH(0x05) | \
328 FTIM2_NAND_TWHRE(0x0f)
329 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
331 #elif defined(CONFIG_TARGET_P1010RDB_PB)
332 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
333 /* ONFI NAND Flash mode0 Timing Params */
334 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
335 FTIM0_NAND_TWP(0x18) | \
336 FTIM0_NAND_TWCHT(0x07) | \
337 FTIM0_NAND_TWH(0x0a))
338 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
339 FTIM1_NAND_TWBE(0x39) | \
340 FTIM1_NAND_TRR(0x0e) | \
341 FTIM1_NAND_TRP(0x18))
342 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
343 FTIM2_NAND_TREH(0x0a) | \
344 FTIM2_NAND_TWHRE(0x1e))
345 #define CONFIG_SYS_NAND_FTIM3 0x0
348 #define CONFIG_SYS_NAND_DDR_LAW 11
350 /* Set up IFC registers for boot location NOR/NAND */
351 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
352 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
353 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
354 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
355 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
356 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
357 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
358 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
359 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
360 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
361 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
362 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
363 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
364 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
365 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
367 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
368 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
369 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
370 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
371 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
372 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
373 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
374 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
375 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
376 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
377 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
378 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
379 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
380 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
384 #define CONFIG_SYS_CPLD_BASE 0xffb00000
386 #ifdef CONFIG_PHYS_64BIT
387 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
389 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
392 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
396 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
397 #define CONFIG_SYS_CSOR3 0x0
398 /* CPLD Timing parameters for IFC CS3 */
399 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
400 FTIM0_GPCM_TEADC(0x0e) | \
401 FTIM0_GPCM_TEAHC(0x0e))
402 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
403 FTIM1_GPCM_TRAD(0x1f))
404 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
405 FTIM2_GPCM_TCH(0x8) | \
406 FTIM2_GPCM_TWP(0x1f))
407 #define CONFIG_SYS_CS3_FTIM3 0x0
409 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
410 defined(CONFIG_RAMBOOT_NAND)
411 #define CONFIG_SYS_RAMBOOT
413 #undef CONFIG_SYS_RAMBOOT
416 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
417 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
418 #define CONFIG_A003399_NOR_WORKAROUND
422 #define CONFIG_SYS_INIT_RAM_LOCK
423 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
424 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
426 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
427 - GENERATED_GBL_DATA_SIZE)
428 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
430 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
433 * Config the L2 Cache as L2 SRAM
435 #if defined(CONFIG_SPL_BUILD)
436 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
437 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
438 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
439 #define CONFIG_SYS_L2_SIZE (256 << 10)
440 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
441 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
442 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
443 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
444 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
445 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
446 #elif defined(CONFIG_MTD_RAW_NAND)
447 #ifdef CONFIG_TPL_BUILD
448 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
449 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
450 #define CONFIG_SYS_L2_SIZE (256 << 10)
451 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
452 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
453 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
454 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
455 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
456 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
458 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
459 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
460 #define CONFIG_SYS_L2_SIZE (256 << 10)
461 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
462 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
463 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
469 #undef CONFIG_SERIAL_SOFTWARE_FIFO
470 #define CONFIG_SYS_NS16550_SERIAL
471 #define CONFIG_SYS_NS16550_REG_SIZE 1
472 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
473 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
474 #define CONFIG_NS16550_MIN_FUNCTIONS
477 #define CONFIG_SYS_BAUDRATE_TABLE \
478 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
480 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
481 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
484 #define I2C_PCA9557_ADDR1 0x18
485 #define I2C_PCA9557_ADDR2 0x19
486 #define I2C_PCA9557_BUS_NUM 0
489 #if defined(CONFIG_TARGET_P1010RDB_PB)
490 #ifdef CONFIG_ID_EEPROM
491 #define CONFIG_SYS_I2C_EEPROM_NXID
493 #define CONFIG_SYS_EEPROM_BUS_NUM 0
494 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
496 /* enable read and write access to EEPROM */
499 #define CONFIG_RTC_PT7C4338
500 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
503 * SPI interface will not be available in case of NAND boot SPI CS0 will be
506 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
507 /* eSPI - Enhanced SPI */
510 #if defined(CONFIG_TSEC_ENET)
511 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
512 #define CONFIG_TSEC1 1
513 #define CONFIG_TSEC1_NAME "eTSEC1"
514 #define CONFIG_TSEC2 1
515 #define CONFIG_TSEC2_NAME "eTSEC2"
516 #define CONFIG_TSEC3 1
517 #define CONFIG_TSEC3_NAME "eTSEC3"
519 #define TSEC1_PHY_ADDR 1
520 #define TSEC2_PHY_ADDR 0
521 #define TSEC3_PHY_ADDR 2
523 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
524 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
525 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
527 #define TSEC1_PHYIDX 0
528 #define TSEC2_PHYIDX 0
529 #define TSEC3_PHYIDX 0
531 #define CONFIG_ETHPRIME "eTSEC1"
533 /* TBI PHY configuration for SGMII mode */
534 #define CONFIG_TSEC_TBICR_SETTINGS ( \
536 | TBICR_ANEG_ENABLE \
537 | TBICR_FULL_DUPLEX \
541 #endif /* CONFIG_TSEC_ENET */
544 #define CONFIG_FSL_SATA_V2
546 #ifdef CONFIG_FSL_SATA
548 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
549 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
551 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
552 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
555 #endif /* #ifdef CONFIG_FSL_SATA */
558 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
561 #define CONFIG_HAS_FSL_DR_USB
563 #if defined(CONFIG_HAS_FSL_DR_USB)
564 #ifdef CONFIG_USB_EHCI_HCD
565 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
572 #if defined(CONFIG_SDCARD)
573 #define CONFIG_FSL_FIXED_MMC_LOCATION
574 #elif defined(CONFIG_MTD_RAW_NAND)
575 #ifdef CONFIG_TPL_BUILD
576 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
578 #if defined(CONFIG_TARGET_P1010RDB_PA)
579 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
580 #elif defined(CONFIG_TARGET_P1010RDB_PB)
581 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
586 #define CONFIG_LOADS_ECHO /* echo on for serial download */
587 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
589 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
590 || defined(CONFIG_FSL_SATA)
594 * Miscellaneous configurable options
598 * For booting Linux, the board info and command line data
599 * have to be in the first 64 MB of memory, since this is
600 * the maximum mapped by the Linux kernel during initialization.
602 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
603 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
606 * Environment Configuration
609 #if defined(CONFIG_TSEC_ENET)
610 #define CONFIG_HAS_ETH0
611 #define CONFIG_HAS_ETH1
612 #define CONFIG_HAS_ETH2
615 #define CONFIG_ROOTPATH "/opt/nfsroot"
616 #define CONFIG_BOOTFILE "uImage"
617 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
619 #define CONFIG_EXTRA_ENV_SETTINGS \
620 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
622 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
623 "loadaddr=1000000\0" \
624 "consoledev=ttyS0\0" \
625 "ramdiskaddr=2000000\0" \
626 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
627 "fdtaddr=1e00000\0" \
628 "fdtfile=p1010rdb.dtb\0" \
630 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
631 "othbootargs=ramdisk_size=600000\0" \
632 "usbfatboot=setenv bootargs root=/dev/ram rw " \
633 "console=$consoledev,$baudrate $othbootargs; " \
635 "fatload usb 0:2 $loadaddr $bootfile;" \
636 "fatload usb 0:2 $fdtaddr $fdtfile;" \
637 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
638 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
639 "usbext2boot=setenv bootargs root=/dev/ram rw " \
640 "console=$consoledev,$baudrate $othbootargs; " \
642 "ext2load usb 0:4 $loadaddr $bootfile;" \
643 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
644 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
645 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
648 #if defined(CONFIG_TARGET_P1010RDB_PA)
649 #define CONFIG_BOOTMODE \
650 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
651 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
652 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
653 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
654 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
655 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
657 #elif defined(CONFIG_TARGET_P1010RDB_PB)
658 #define CONFIG_BOOTMODE \
659 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
660 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
661 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
662 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
663 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
664 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
665 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
666 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
667 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
668 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
671 #include <asm/fsl_secure_boot.h>
673 #endif /* __CONFIG_H */