2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC855 1 /* This is a MPC855 CPU */
37 #define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
40 #define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */
42 #define CONFIG_66MHz 1 /* running at 66 MHz, 1:1 clock */
44 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
46 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
48 #define CONFIG_BOARD_TYPES 1 /* support board types */
50 #define CONFIG_PREBOOT "echo;" \
51 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
54 #undef CONFIG_BOOTARGS
56 #define CONFIG_EXTRA_ENV_SETTINGS \
58 "nfsargs=setenv bootargs root=/dev/nfs rw " \
59 "nfsroot=${serverip}:${rootpath}\0" \
60 "ramargs=setenv bootargs root=/dev/ram rw\0" \
61 "addip=setenv bootargs ${bootargs} " \
62 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
63 ":${hostname}:${netdev}:off panic=1\0" \
64 "flash_nfs=run nfsargs addip;" \
65 "bootm ${kernel_addr}\0" \
66 "flash_self=run ramargs addip;" \
67 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
68 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
69 "rootpath=/opt/eldk/ppc_8xx\0" \
70 "bootfile=/tftpboot/NSCU/uImage\0" \
71 "kernel_addr=40080000\0" \
72 "ramdisk_addr=40180000\0" \
74 #define CONFIG_BOOTCOMMAND "run flash_self"
76 #define CONFIG_MISC_INIT_R 1
78 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
79 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
81 #undef CONFIG_WATCHDOG /* watchdog disabled */
83 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
85 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
87 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
89 #define CONFIG_MAC_PARTITION
90 #define CONFIG_DOS_PARTITION
92 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
94 #define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */
96 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
104 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
105 #include <cmd_confdefs.h>
108 * Miscellaneous configurable options
110 #define CFG_LONGHELP /* undef to save memory */
111 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
114 #define CFG_HUSH_PARSER 1 /* use "hush" command parser */
116 #ifdef CFG_HUSH_PARSER
117 #define CFG_PROMPT_HUSH_PS2 "> "
120 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
121 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
123 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
125 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
126 #define CFG_MAXARGS 16 /* max number of command args */
127 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
129 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
130 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
132 #define CFG_LOAD_ADDR 0x100000 /* default load address */
134 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
136 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
139 * Low Level Configuration Settings
140 * (address mappings, register initial values, etc.)
141 * You should know what you are doing if you make changes here.
143 /*-----------------------------------------------------------------------
144 * Internal Memory Mapped Register
146 #define CFG_IMMR 0xFFF00000
148 /*-----------------------------------------------------------------------
149 * Definitions for initial stack pointer and data area (in DPRAM)
151 #define CFG_INIT_RAM_ADDR CFG_IMMR
152 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
153 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
154 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
155 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
157 /*-----------------------------------------------------------------------
158 * Start addresses for the final memory configuration
159 * (Set up by the startup code)
160 * Please note that CFG_SDRAM_BASE _must_ start at 0
162 #define CFG_SDRAM_BASE 0x00000000
163 #define CFG_FLASH_BASE 0x40000000
164 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
165 #define CFG_MONITOR_BASE CFG_FLASH_BASE
166 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
169 * For booting Linux, the board info and command line data
170 * have to be in the first 8 MB of memory, since this is
171 * the maximum mapped by the Linux kernel during initialization.
173 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
175 /*-----------------------------------------------------------------------
178 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
179 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
181 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
182 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
184 #define CFG_ENV_IS_IN_FLASH 1
185 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
186 #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
187 #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
189 /* Address and size of Redundant Environment Sector */
190 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
191 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
193 /*-----------------------------------------------------------------------
194 * Hardware Information Block
196 #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
197 #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
198 #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
200 /*-----------------------------------------------------------------------
201 * Cache Configuration
203 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
204 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
205 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
208 /*-----------------------------------------------------------------------
209 * SYPCR - System Protection Control 11-9
210 * SYPCR can only be written once after reset!
211 *-----------------------------------------------------------------------
212 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
214 #if defined(CONFIG_WATCHDOG)
215 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
216 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
218 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
221 /*-----------------------------------------------------------------------
222 * SIUMCR - SIU Module Configuration 11-6
223 *-----------------------------------------------------------------------
224 * PCMCIA config., multi-function pin tri-state
226 #ifndef CONFIG_CAN_DRIVER
227 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
228 #else /* we must activate GPL5 in the SIUMCR for CAN */
229 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
230 #endif /* CONFIG_CAN_DRIVER */
232 /*-----------------------------------------------------------------------
233 * TBSCR - Time Base Status and Control 11-26
234 *-----------------------------------------------------------------------
235 * Clear Reference Interrupt Status, Timebase freezing enabled
237 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
239 /*-----------------------------------------------------------------------
240 * RTCSC - Real-Time Clock Status and Control Register 11-27
241 *-----------------------------------------------------------------------
243 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
245 /*-----------------------------------------------------------------------
246 * PISCR - Periodic Interrupt Status and Control 11-31
247 *-----------------------------------------------------------------------
248 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
250 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
252 /*-----------------------------------------------------------------------
253 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
254 *-----------------------------------------------------------------------
255 * Reset PLL lock status sticky bit, timer expired status bit and timer
256 * interrupt status bit
258 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
260 /*-----------------------------------------------------------------------
261 * SCCR - System Clock and reset Control Register 15-27
262 *-----------------------------------------------------------------------
263 * Set clock output, timebase and RTC source and divider,
264 * power management and some other internal clocks
266 #define SCCR_MASK SCCR_EBDF11
267 #define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
268 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
271 /*-----------------------------------------------------------------------
273 *-----------------------------------------------------------------------
276 /* NSCU use both slots, SLOT_A as "primary". */
277 #define CONFIG_PCMCIA_SLOT_A 1
279 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
280 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
281 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
282 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
283 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
284 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
285 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
286 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
287 #define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */
288 #define PCMCIA_SOCKETS_NO 2 /* we have two sockets */
289 #undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */
291 /*-----------------------------------------------------------------------
292 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
293 *-----------------------------------------------------------------------
296 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
298 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
299 #undef CONFIG_IDE_LED /* LED for ide not supported */
300 #undef CONFIG_IDE_RESET /* reset for ide not supported */
302 #define CFG_IDE_MAXBUS 2 /* max. 2 IDE buses */
303 #define CFG_IDE_MAXDEVICE 4 /* max. 2 drives per IDE bus */
305 #define CFG_ATA_IDE0_OFFSET 0x0000
306 #define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE) /* starts @ 4th window */
308 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
310 /* Offset for data I/O */
311 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
313 /* Offset for normal register accesses */
314 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
316 /* Offset for alternate registers */
317 #define CFG_ATA_ALT_OFFSET 0x0100
319 /*-----------------------------------------------------------------------
321 *-----------------------------------------------------------------------
327 * Init Memory Controller:
329 * BR0/1 and OR0/1 (FLASH)
332 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
333 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
335 /* used to re-map FLASH both when starting from SRAM or FLASH:
336 * restrict access enough to keep SRAM working (if any)
337 * but not too much to meddle with FLASH accesses
339 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
340 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
345 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
346 OR_SCY_3_CLK | OR_EHTR | OR_BI)
348 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
349 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
350 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
352 #define CFG_OR1_REMAP CFG_OR0_REMAP
353 #define CFG_OR1_PRELIM CFG_OR0_PRELIM
354 #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
357 * BR2/3 and OR2/3 (SDRAM)
360 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
361 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
362 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
364 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
365 #define CFG_OR_TIMING_SDRAM 0x00000A00
367 #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
368 #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
370 #ifndef CONFIG_CAN_DRIVER
371 #define CFG_OR3_PRELIM CFG_OR2_PRELIM
372 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
373 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
374 #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
375 #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
376 #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
377 #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
378 BR_PS_8 | BR_MS_UPMB | BR_V )
379 #endif /* CONFIG_CAN_DRIVER */
381 #ifdef CONFIG_ISP1362_USB
382 #define CFG_ISP1362_BASE 0xD0000000 /* ISP1362 mapped at 0xD0000000 */
383 #define CFG_ISP1362_OR_AM 0xFFFF8000 /* 32 kB address mask */
384 #define CFG_OR5_ISP1362 (CFG_ISP1362_OR_AM | OR_CSNT_SAM | \
385 OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK)
386 #define CFG_BR5_ISP1362 ((CFG_ISP1362_BASE & BR_BA_MSK) | \
387 BR_PS_16 | BR_MS_GPCM | BR_V )
388 #endif /* CONFIG_ISP1362_USB */
391 * Memory Periodic Timer Prescaler
393 * The Divider for PTA (refresh timer) configuration is based on an
394 * example SDRAM configuration (64 MBit, one bank). The adjustment to
395 * the number of chip selects (NCS) and the actually needed refresh
396 * rate is done by setting MPTPR.
398 * PTA is calculated from
399 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
401 * gclk CPU clock (not bus clock!)
402 * Trefresh Refresh cycle * 4 (four word bursts used)
404 * 4096 Rows from SDRAM example configuration
405 * 1000 factor s -> ms
406 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
407 * 4 Number of refresh cycles per period
408 * 64 Refresh cycle in ms per number of rows
409 * --------------------------------------------
410 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
412 * 50 MHz => 50.000.000 / Divider = 98
413 * 66 Mhz => 66.000.000 / Divider = 129
414 * 80 Mhz => 80.000.000 / Divider = 156
417 #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
418 #define CFG_MAMR_PTA 98
421 * For 16 MBit, refresh rates could be 31.3 us
422 * (= 64 ms / 2K = 125 / quad bursts).
423 * For a simpler initialization, 15.6 us is used instead.
425 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
426 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
428 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
429 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
431 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
432 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
433 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
436 * MAMR settings for SDRAM
440 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
441 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
442 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
444 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
445 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
446 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
450 * Internal Definitions
454 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
455 #define BOOTFLAG_WARM 0x02 /* Software reboot */
457 #undef CONFIG_SCC1_ENET
458 #define CONFIG_FEC_ENET
459 /* #define CONFIG_ETHPRIME "FEC ETHERNET" */
461 #endif /* __CONFIG_H */