2 * (C) Copyright 2000-2010
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
26 * U-Boot port on NetTA4 board
33 * High Level Configuration Options
37 #define CONFIG_MPC885 1 /* This is a MPC885 CPU */
38 #define CONFIG_NETTA 1 /* ...on a NetTA board */
40 #define CONFIG_SYS_TEXT_BASE 0x40000000
42 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
43 #undef CONFIG_8xx_CONS_SMC2
44 #undef CONFIG_8xx_CONS_NONE
46 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
48 /* #define CONFIG_XIN 10000000 */
49 #define CONFIG_XIN 50000000
50 #define MPC8XX_HZ 120000000
51 /* #define MPC8XX_HZ 100000000 */
52 /* #define MPC8XX_HZ 50000000 */
53 /* #define MPC8XX_HZ 80000000 */
55 #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
58 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
60 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
63 #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
65 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
67 #undef CONFIG_BOOTARGS
68 #define CONFIG_BOOTCOMMAND \
70 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
74 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
75 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
77 #undef CONFIG_WATCHDOG /* watchdog disabled */
78 #define CONFIG_HW_WATCHDOG
80 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
85 #define CONFIG_BOOTP_SUBNETMASK
86 #define CONFIG_BOOTP_GATEWAY
87 #define CONFIG_BOOTP_HOSTNAME
88 #define CONFIG_BOOTP_BOOTPATH
89 #define CONFIG_BOOTP_BOOTFILESIZE
90 #define CONFIG_BOOTP_NISDOMAIN
93 #undef CONFIG_MAC_PARTITION
94 #undef CONFIG_DOS_PARTITION
96 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
98 #define FEC_ENET 1 /* eth.c needs it that way... */
99 #undef CONFIG_SYS_DISCOVER_PHY /* do not discover phys */
101 #define CONFIG_MII_INIT 1
102 #define CONFIG_RMII 1 /* use RMII interface */
104 #if defined(CONFIG_NETTA_ISDN)
105 #define CONFIG_ETHER_ON_FEC1 1
106 #define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */
107 #define CONFIG_FEC1_PHY_NORXERR 1
108 #undef CONFIG_ETHER_ON_FEC2
110 #define CONFIG_ETHER_ON_FEC1 1
111 #define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */
112 #define CONFIG_FEC1_PHY_NORXERR 1
113 #define CONFIG_ETHER_ON_FEC2 1
114 #define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */
115 #define CONFIG_FEC2_PHY_NORXERR 1
118 #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
121 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
122 CONFIG_SYS_POST_CODEC | \
123 CONFIG_SYS_POST_DSP )
127 * Command line configuration.
129 #include <config_cmd_default.h>
131 #define CONFIG_CMD_CDP
132 #define CONFIG_CMD_DHCP
133 #define CONFIG_CMD_DIAG
134 #define CONFIG_CMD_FAT
135 #define CONFIG_CMD_IDE
136 #define CONFIG_CMD_JFFS2
137 #define CONFIG_CMD_MII
138 #define CONFIG_CMD_NFS
139 #define CONFIG_CMD_PCMCIA
140 #define CONFIG_CMD_PING
143 #define CONFIG_BOARD_EARLY_INIT_F 1
144 #define CONFIG_MISC_INIT_R
147 * Miscellaneous configurable options
149 #define CONFIG_SYS_LONGHELP /* undef to save memory */
150 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
152 #define CONFIG_SYS_HUSH_PARSER 1
154 #if defined(CONFIG_CMD_KGDB)
155 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
157 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
159 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
160 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
161 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
163 #define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
164 #define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
166 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
168 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
171 * Low Level Configuration Settings
172 * (address mappings, register initial values, etc.)
173 * You should know what you are doing if you make changes here.
175 /*-----------------------------------------------------------------------
176 * Internal Memory Mapped Register
178 #define CONFIG_SYS_IMMR 0xFF000000
180 /*-----------------------------------------------------------------------
181 * Definitions for initial stack pointer and data area (in DPRAM)
183 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
184 #define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
185 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
186 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
188 /*-----------------------------------------------------------------------
189 * Start addresses for the final memory configuration
190 * (Set up by the startup code)
191 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
193 #define CONFIG_SYS_SDRAM_BASE 0x00000000
194 #define CONFIG_SYS_FLASH_BASE 0x40000000
196 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
198 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
200 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
201 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
204 * For booting Linux, the board info and command line data
205 * have to be in the first 8 MB of memory, since this is
206 * the maximum mapped by the Linux kernel during initialization.
208 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
210 /*-----------------------------------------------------------------------
213 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
214 #define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
216 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
217 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
219 #define CONFIG_ENV_IS_IN_FLASH 1
220 #define CONFIG_ENV_SECT_SIZE 0x10000
222 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
223 #define CONFIG_ENV_SIZE 0x4000
225 #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
226 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
228 /*-----------------------------------------------------------------------
229 * Cache Configuration
231 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
232 #if defined(CONFIG_CMD_KGDB)
233 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
236 /*-----------------------------------------------------------------------
237 * SYPCR - System Protection Control 11-9
238 * SYPCR can only be written once after reset!
239 *-----------------------------------------------------------------------
240 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
242 #if defined(CONFIG_WATCHDOG)
243 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
244 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
246 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
249 /*-----------------------------------------------------------------------
250 * SIUMCR - SIU Module Configuration 11-6
251 *-----------------------------------------------------------------------
252 * PCMCIA config., multi-function pin tri-state
254 #ifndef CONFIG_CAN_DRIVER
255 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
256 #else /* we must activate GPL5 in the SIUMCR for CAN */
257 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
258 #endif /* CONFIG_CAN_DRIVER */
260 /*-----------------------------------------------------------------------
261 * TBSCR - Time Base Status and Control 11-26
262 *-----------------------------------------------------------------------
263 * Clear Reference Interrupt Status, Timebase freezing enabled
265 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
267 /*-----------------------------------------------------------------------
268 * RTCSC - Real-Time Clock Status and Control Register 11-27
269 *-----------------------------------------------------------------------
271 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
273 /*-----------------------------------------------------------------------
274 * PISCR - Periodic Interrupt Status and Control 11-31
275 *-----------------------------------------------------------------------
276 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
278 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
280 /*-----------------------------------------------------------------------
281 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
282 *-----------------------------------------------------------------------
283 * Reset PLL lock status sticky bit, timer expired status bit and timer
284 * interrupt status bit
288 #if CONFIG_XIN == 10000000
290 #if MPC8XX_HZ == 120000000
291 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
292 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
294 #elif MPC8XX_HZ == 100000000
295 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
296 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
298 #elif MPC8XX_HZ == 50000000
299 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
300 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
302 #elif MPC8XX_HZ == 25000000
303 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
304 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
306 #elif MPC8XX_HZ == 40000000
307 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
308 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
310 #elif MPC8XX_HZ == 75000000
311 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
312 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
315 #error unsupported CPU freq for XIN = 10MHz
318 #elif CONFIG_XIN == 50000000
320 #if MPC8XX_HZ == 120000000
321 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
322 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
324 #elif MPC8XX_HZ == 100000000
325 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
326 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
328 #elif MPC8XX_HZ == 80000000
329 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
330 (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
332 #elif MPC8XX_HZ == 50000000
333 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
334 (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
337 #error unsupported CPU freq for XIN = 50MHz
342 #error unsupported XIN freq
347 *-----------------------------------------------------------------------
348 * SCCR - System Clock and reset Control Register 15-27
349 *-----------------------------------------------------------------------
350 * Set clock output, timebase and RTC source and divider,
351 * power management and some other internal clocks
353 * Note: When TBS == 0 the timebase is independent of current cpu clock.
356 #define SCCR_MASK SCCR_EBDF11
357 #if MPC8XX_HZ > 66666666
358 #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
359 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
360 SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
361 SCCR_DFALCD00 | SCCR_EBDF01)
363 #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
364 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
365 SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
369 /*-----------------------------------------------------------------------
371 *-----------------------------------------------------------------------
374 /*#define CONFIG_SYS_DER 0x2002000F*/
375 #define CONFIG_SYS_DER 0
378 * Init Memory Controller:
380 * BR0/1 and OR0/1 (FLASH)
383 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
385 /* used to re-map FLASH both when starting from SRAM or FLASH:
386 * restrict access enough to keep SRAM working (if any)
387 * but not too much to meddle with FLASH accesses
389 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
390 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
392 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
393 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
395 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
396 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
397 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
400 * BR3 and OR3 (SDRAM)
403 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
404 #define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
406 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
407 #define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
409 #define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
410 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
413 * Memory Periodic Timer Prescaler
417 * Memory Periodic Timer Prescaler
419 * The Divider for PTA (refresh timer) configuration is based on an
420 * example SDRAM configuration (64 MBit, one bank). The adjustment to
421 * the number of chip selects (NCS) and the actually needed refresh
422 * rate is done by setting MPTPR.
424 * PTA is calculated from
425 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
427 * gclk CPU clock (not bus clock!)
428 * Trefresh Refresh cycle * 4 (four word bursts used)
430 * 4096 Rows from SDRAM example configuration
431 * 1000 factor s -> ms
432 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
433 * 4 Number of refresh cycles per period
434 * 64 Refresh cycle in ms per number of rows
435 * --------------------------------------------
436 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
438 * 50 MHz => 50.000.000 / Divider = 98
439 * 66 Mhz => 66.000.000 / Divider = 129
440 * 80 Mhz => 80.000.000 / Divider = 156
443 #if MPC8XX_HZ == 120000000
444 #define CONFIG_SYS_MAMR_PTA 234
445 #elif MPC8XX_HZ == 100000000
446 #define CONFIG_SYS_MAMR_PTA 195
447 #elif MPC8XX_HZ == 80000000
448 #define CONFIG_SYS_MAMR_PTA 156
449 #elif MPC8XX_HZ == 50000000
450 #define CONFIG_SYS_MAMR_PTA 98
452 #error Unknown frequency
457 * For 16 MBit, refresh rates could be 31.3 us
458 * (= 64 ms / 2K = 125 / quad bursts).
459 * For a simpler initialization, 15.6 us is used instead.
461 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
462 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
464 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
465 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
467 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
468 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
469 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
472 * MAMR settings for SDRAM
476 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
477 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
478 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
481 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
482 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
483 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
485 #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
487 /***********************************************************************************************************
491 +------+----------------+--------+------------------------------------------------------------
492 | # | Name | Type | Comment
493 +------+----------------+--------+------------------------------------------------------------
494 | PA3 | OK_ETH_3V | Input | CISCO Ethernet power OK
495 | | | | (NetRoute: FEC1, TA: FEC2) (0=power OK)
496 | PA6 | P_VCCD1 | Output | TPS2211A PCMCIA
497 | PA7 | DCL1_3V | Periph | IDL1 PCM clock
498 | PA8 | DSP_DR1 | Periph | IDL1 PCM Data Rx
499 | PA9 | L1TXDA | Periph | IDL1 PCM Data Tx
500 | PA10 | P_VCCD0 | Output | TPS2211A PCMCIA
501 | PA12 | P_SHDN | Output | TPS2211A PCMCIA
502 | PA13 | ETH_LOOP | Output | CISCO Loopback remote power
503 | | | | (NetRoute: FEC1, TA: FEC2) (1=NORMAL)
504 | PA14 | P_VPPD0 | Output | TPS2211A PCMCIA
505 | PA15 | P_VPPD1 | Output | TPS2211A PCMCIA
506 | PB14 | SPIEN_FXO | Output | SPI CS for FXO daughter-board
507 | PB15 | SPIEN_S1 | Output | SPI CS for S-interface 1 (NetRoute only)
508 | PB16 | DREQ1 | Output | D channel request for S-interface chip 1.
509 | PB17 | L1ST3 | Periph | IDL1 timeslot enable signal for PPC
510 | PB18 | L1ST2 | Periph | IDL1 timeslot enable signal for PPC
511 | PB19 | SPIEN_S2 | Output | SPI CS for S-interface 2 (NetRoute only)
512 | PB20 | SPIEN_SEEPROM | Output | SPI CS for serial eeprom
513 | PB21 | LEDIO | Output | Led mode indication for PHY
514 | PB22 | UART_CTS | Input | UART CTS
515 | PB23 | UART_RTS | Output | UART RTS
516 | PB24 | UART_RX | Periph | UART Data Rx
517 | PB25 | UART_TX | Periph | UART Data Tx
518 | PB26 | RMII-MDC | Periph | Free for future use (MII mgt clock)
519 | PB27 | RMII-MDIO | Periph | Free for future use (MII mgt data)
520 | PB28 | SPI_RXD_3V | Input | SPI Data Rx
521 | PB29 | SPI_TXD | Output | SPI Data Tx
522 | PB30 | SPI_CLK | Output | SPI Clock
523 | PB31 | RMII1-REFCLK | Periph | RMII reference clock for FEC1
524 | PC4 | PHY1_LINK | Input | PHY link state FEC1 (interrupt)
525 | PC5 | PHY2_LINK | Input | PHY link state FEC2 (interrupt)
526 | PC6 | RMII1-MDINT | Input | PHY prog interrupt FEC1 (interrupt)
527 | PC7 | RMII2-MDINT | Input | PHY prog interrupt FEC1 (interrupt)
528 | PC8 | P_OC | Input | TPS2211A PCMCIA overcurrent (interrupt) (1=OK)
529 | PC9 | COM_HOOK1 | Input | Codec interrupt chip #1 (interrupt)
530 | PC10 | COM_HOOK2 | Input | Codec interrupt chip #2 (interrupt)
531 | PC11 | COM_HOOK4 | Input | Codec interrupt chip #4 (interrupt)
532 | PC12 | COM_HOOK3 | Input | Codec interrupt chip #3 (interrupt)
533 | PC13 | F_RY_BY | Input | NAND ready signal (interrupt)
534 | PC14 | FAN_OK | Input | Fan status signal (interrupt) (1=OK)
535 | PC15 | PC15_DIRECT0 | Periph | PCMCIA DMA request.
536 | PD3 | F_ALE | Output | NAND
537 | PD4 | F_CLE | Output | NAND
538 | PD5 | F_CE | Output | NAND
539 | PD6 | DSP_INT | Output | DSP debug interrupt
540 | PD7 | DSP_RESET | Output | DSP reset
541 | PD8 | RMII_MDC | Periph | MII mgt clock
542 | PD9 | SPIEN_C1 | Output | SPI CS for codec #1
543 | PD10 | SPIEN_C2 | Output | SPI CS for codec #2
544 | PD11 | SPIEN_C3 | Output | SPI CS for codec #3
545 | PD12 | FSC2 | Periph | IDL2 frame sync
546 | PD13 | DGRANT2 | Input | D channel grant from S #2
547 | PD14 | SPIEN_C4 | Output | SPI CS for codec #4
548 | PD15 | TP700 | Output | Testpoint for software debugging
549 | PE14 | RMII2-TXD0 | Periph | FEC2 transmit data
550 | PE15 | RMII2-TXD1 | Periph | FEC2 transmit data
551 | PE16 | RMII2-REFCLK | Periph | TA: RMII ref clock for
552 | | DCL2 | Periph | NetRoute: PCM clock #2
553 | PE17 | TP703 | Output | Testpoint for software debugging
554 | PE18 | DGRANT1 | Input | D channel grant from S #1
555 | PE19 | RMII2-TXEN | Periph | TA: FEC2 tx enable
556 | | PCM2OUT | Periph | NetRoute: Tx data for IDL2
557 | PE20 | FSC1 | Periph | IDL1 frame sync
558 | PE21 | RMII2-RXD0 | Periph | FEC2 receive data
559 | PE22 | RMII2-RXD1 | Periph | FEC2 receive data
560 | PE23 | L1ST1 | Periph | IDL1 timeslot enable signal for PPC
561 | PE24 | U-N1 | Output | Select user/network for S #1 (0=user)
562 | PE25 | U-N2 | Output | Select user/network for S #2 (0=user)
563 | PE26 | RMII2-RXDV | Periph | FEC2 valid
564 | PE27 | DREQ2 | Output | D channel request for S #2.
565 | PE28 | FPGA_DONE | Input | FPGA done signal
566 | PE29 | FPGA_INIT | Output | FPGA init signal
567 | PE30 | UDOUT2_3V | Input | IDL2 PCM input
569 +------+----------------+--------+---------------------------------------------------
573 +------+----------------+------------------------------------------------------------
575 +------+----------------+------------------------------------------------------------
576 | CS0 | CS0 | Boot flash
577 | CS1 | CS_FLASH | NAND flash
579 | CS3 | DCS_DRAM | DRAM
580 | CS4 | CS_ER1 | External output register
581 +------+----------------+------------------------------------------------------------
585 +------+----------------+------------------------------------------------------------
587 +------+----------------+------------------------------------------------------------
588 | IRQ1 | UINTER_3V | S interrupt chips interrupt (common)
589 | IRQ3 | IRQ_DSP | DSP interrupt
590 | IRQ4 | IRQ_DSP1 | Extra DSP interrupt
591 +------+----------------+------------------------------------------------------------
593 *************************************************************************************************/
595 #define DSP_SIZE 0x00010000 /* 64K */
596 #define NAND_SIZE 0x00010000 /* 64K */
597 #define ER_SIZE 0x00010000 /* 64K */
598 #define DUMMY_SIZE 0x00010000 /* 64K */
600 #define DSP_BASE 0xF1000000
601 #define NAND_BASE 0xF1010000
602 #define ER_BASE 0xF1020000
603 #define DUMMY_BASE 0xF1FF0000
605 /*****************************************************************************/
607 #define CONFIG_SYS_DIRECT_FLASH_TFTP
608 #define CONFIG_SYS_DIRECT_NAND_TFTP
610 /*****************************************************************************/
613 /*-----------------------------------------------------------------------
615 *-----------------------------------------------------------------------
618 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
619 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
620 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
621 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
622 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
623 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
624 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
625 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
627 /*-----------------------------------------------------------------------
628 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
629 *-----------------------------------------------------------------------
632 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
634 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
635 #undef CONFIG_IDE_LED /* LED for ide not supported */
636 #undef CONFIG_IDE_RESET /* reset for ide not supported */
638 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
639 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
641 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
643 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
645 /* Offset for data I/O */
646 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
648 /* Offset for normal register accesses */
649 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
651 /* Offset for alternate registers */
652 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
654 #define CONFIG_MAC_PARTITION
655 #define CONFIG_DOS_PARTITION
658 /*************************************************************************************************/
660 #define CONFIG_CDP_DEVICE_ID 20
661 #define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta */
662 #define CONFIG_CDP_PORT_ID "eth%d"
663 #define CONFIG_CDP_CAPABILITIES 0x00000010
664 #define CONFIG_CDP_VERSION "u-boot 1.0" " " U_BOOT_DATE " " U_BOOT_TIME
665 #define CONFIG_CDP_PLATFORM "Intracom NetTA"
666 #define CONFIG_CDP_TRIGGER 0x20020001
667 #define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
668 #define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone? */
670 /*************************************************************************************************/
672 #define CONFIG_AUTO_COMPLETE 1
674 /*************************************************************************************************/
676 #define CONFIG_CRC32_VERIFY 1
678 /*************************************************************************************************/
680 #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
682 /*************************************************************************************************/
684 #endif /* __CONFIG_H */