2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2004-2010
6 * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #define CONFIG_MPC5xxx 1
33 #define CONFIG_MPC5200 1
35 #ifndef CONFIG_SYS_TEXT_BASE
36 #define CONFIG_SYS_TEXT_BASE 0xFF800000
39 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000
41 #define CONFIG_MISC_INIT_R 1
43 #define CONFIG_SYS_CACHELINE_SIZE 32
44 #ifdef CONFIG_CMD_KGDB
45 #define CONFIG_SYS_CACHELINE_SHIFT 5
48 #define CONFIG_PSC_CONSOLE 1
49 #define CONFIG_BAUDRATE 115200
50 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200,\
54 #define CONFIG_PCI_PNP 1
55 #undef CONFIG_PCI_SCAN_SHOW
56 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
58 #define CONFIG_PCI_MEM_BUS 0x40000000
59 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
60 #define CONFIG_PCI_MEM_SIZE 0x10000000
62 #define CONFIG_PCI_IO_BUS 0x50000000
63 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
64 #define CONFIG_PCI_IO_SIZE 0x01000000
66 #define CONFIG_SYS_XLB_PIPELINING 1
67 #define CONFIG_HIGH_BATS 1
71 #define MV_FPGA_DATA 0xff840000
72 #define MV_FPGA_SIZE 0x1ff88
73 #define MV_KERNEL_ADDR 0xfff00000
74 #define MV_SCRIPT_ADDR 0xff806000
75 #define MV_INITRD_ADDR 0xff880000
76 #define MV_INITRD_LENGTH 0x00240000
77 #define MV_SCRATCH_ADDR 0xffcc0000
78 #define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
80 #define CONFIG_SHOW_BOOT_PROGRESS 1
82 #define MV_KERNEL_ADDR_RAM 0x00100000
83 #define MV_INITRD_ADDR_RAM 0x00400000
88 #include <config_cmd_default.h>
90 #define CONFIG_CMD_CACHE
91 #define CONFIG_CMD_DHCP
92 #define CONFIG_CMD_FPGA
93 #define CONFIG_CMD_I2C
94 #define CONFIG_CMD_MII
95 #define CONFIG_CMD_NET
96 #define CONFIG_CMD_PCI
97 #define CONFIG_CMD_PING
98 #define CONFIG_CMD_SDRAM
100 #define CONFIG_BOOTP_BOOTFILESIZE
101 #define CONFIG_BOOTP_BOOTPATH
102 #define CONFIG_BOOTP_DNS
103 #define CONFIG_BOOTP_DNS2
104 #define CONFIG_BOOTP_GATEWAY
105 #define CONFIG_BOOTP_HOSTNAME
106 #define CONFIG_BOOTP_NTPSERVER
107 #define CONFIG_BOOTP_RANDOM_DELAY
108 #define CONFIG_BOOTP_SEND_HOSTNAME
109 #define CONFIG_BOOTP_SUBNETMASK
110 #define CONFIG_BOOTP_VENDOREX
115 #define CONFIG_BOOTDELAY 1
116 #define CONFIG_AUTOBOOT_KEYED
117 #define CONFIG_AUTOBOOT_STOP_STR "abcdefg"
118 #define CONFIG_ZERO_BOOTDELAY_CHECK
120 #define CONFIG_BOOTCOMMAND "source ${script_addr}"
121 #define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" \
124 #define XMK_STR(x) #x
125 #define MK_STR(x) XMK_STR(x)
127 #define CONFIG_EXTRA_ENV_SETTINGS \
134 "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
135 "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
136 "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
137 "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
138 "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
139 "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
140 "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
141 "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
142 "mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \
143 "mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \
144 "mv_version=" U_BOOT_VERSION "\0" \
145 "dhcp_client_id=" MK_STR(MV_CI) "\0" \
146 "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
148 "use_static_ipaddr=no\0" \
149 "static_ipaddr=192.168.0.101\0" \
150 "static_netmask=255.255.255.0\0" \
151 "static_gateway=0.0.0.0\0" \
152 "initrd_name=uInitrd.mvsmr-rfs\0" \
161 * IPB Bus clocking configuration.
163 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
166 * Flash configuration
168 #undef CONFIG_FLASH_16BIT
169 #define CONFIG_SYS_FLASH_CFI
170 #define CONFIG_FLASH_CFI_DRIVER
171 #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
172 #define CONFIG_SYS_FLASH_EMPTY_INFO
174 #define CONFIG_SYS_FLASH_ERASE_TOUT 50000
175 #define CONFIG_SYS_FLASH_WRITE_TOUT 1000
177 #define CONFIG_SYS_MAX_FLASH_BANKS 1
178 #define CONFIG_SYS_MAX_FLASH_SECT 256
180 #define CONFIG_SYS_LOWBOOT
181 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
182 #define CONFIG_SYS_FLASH_SIZE 0x00800000
185 * Environment settings
187 #define CONFIG_ENV_IS_IN_FLASH
188 #undef CONFIG_SYS_FLASH_PROTECTION
189 #define CONFIG_OVERWRITE_ETHADDR_ONCE
191 #define CONFIG_ENV_OFFSET 0x8000
192 #define CONFIG_ENV_SIZE 0x2000
193 #define CONFIG_ENV_SECT_SIZE 0x2000
195 /* used by linker script to wrap code around */
196 #define CONFIG_SCRIPT_OFFSET 0x6000
197 #define CONFIG_SCRIPT_SECT_SIZE 0x2000
202 #define CONFIG_SYS_MBAR 0xF0000000
203 #define CONFIG_SYS_SDRAM_BASE 0x00000000
204 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
206 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
207 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
209 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
210 GENERATED_GBL_DATA_SIZE)
211 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
213 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
214 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
215 #define CONFIG_SYS_RAMBOOT 1
218 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
219 #define CONFIG_SYS_MONITOR_LEN (512 << 10)
220 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
221 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
226 #define CONFIG_HARD_I2C 1
227 #define CONFIG_SYS_I2C_MODULE 1
228 #define CONFIG_SYS_I2C_SPEED 86000
229 #define CONFIG_SYS_I2C_SLAVE 0x7F
232 * Ethernet configuration
234 #define CONFIG_NET_RETRY_COUNT 5
236 #define CONFIG_MPC5xxx_FEC
237 #define CONFIG_MPC5xxx_FEC_MII100
238 #define CONFIG_PHY_ADDR 0x00
239 #define CONFIG_NETDEV eth0
242 * Miscellaneous configurable options
244 #define CONFIG_SYS_HUSH_PARSER
245 #define CONFIG_CMDLINE_EDITING
246 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
247 #undef CONFIG_SYS_LONGHELP
248 #define CONFIG_SYS_PROMPT "=> "
249 #ifdef CONFIG_CMD_KGDB
250 #define CONFIG_SYS_CBSIZE 1024
252 #define CONFIG_SYS_CBSIZE 256
254 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
255 #define CONFIG_SYS_MAXARGS 16
256 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
258 #define CONFIG_SYS_MEMTEST_START 0x00800000
259 #define CONFIG_SYS_MEMTEST_END 0x02f00000
261 #define CONFIG_SYS_HZ 1000
263 /* default load address */
264 #define CONFIG_SYS_LOAD_ADDR 0x02000000
265 /* default location for tftp and bootm */
266 #define CONFIG_LOADADDR 0x00200000
269 * Various low-level settings
271 #define CONFIG_SYS_GPS_PORT_CONFIG 0x00050044
273 #define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
274 #define CONFIG_SYS_HID0_FINAL HID0_ICE
276 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
277 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
278 #define CONFIG_SYS_BOOTCS_CFG 0x00047800
279 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
280 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
282 #define CONFIG_SYS_CS_BURST 0x000000f0
283 #define CONFIG_SYS_CS_DEADCYCLE 0x33333303
285 #define CONFIG_SYS_RESET_ADDRESS 0x00000100
288 #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
289 #define CONFIG_FPGA CONFIG_SYS_XILINX_SPARTAN2
290 #define CONFIG_FPGA_XILINX 1
291 #define CONFIG_FPGA_SPARTAN2 1
292 #define CONFIG_FPGA_COUNT 1