include/configs/MVSMR.h

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004-2010
   6  * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include <version.h>
  15
  16 #define CONFIG_MPC5200  1
  17
  18 #ifndef CONFIG_SYS_TEXT_BASE
  19 #define CONFIG_SYS_TEXT_BASE    0xFF800000
  20 #endif
  21 #define CONFIG_SYS_LDSCRIPT     "board/matrix_vision/mvsmr/u-boot.lds"
  22
  23 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000
  24
  25 #define CONFIG_MISC_INIT_R      1
  26
  27 #define CONFIG_SYS_CACHELINE_SIZE       32
  28 #ifdef CONFIG_CMD_KGDB
  29 #define CONFIG_SYS_CACHELINE_SHIFT      5
  30 #endif
  31
  32 #define CONFIG_PSC_CONSOLE      1
  33 #define CONFIG_BAUDRATE         115200
  34 #define CONFIG_SYS_BAUDRATE_TABLE       {9600, 19200, 38400, 57600, 115200,\
  35                                                 230400}
  36
  37 #define CONFIG_PCI              1
  38 #define CONFIG_PCI_PNP          1
  39 #undef  CONFIG_PCI_SCAN_SHOW
  40 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  41
  42 #define CONFIG_PCI_MEM_BUS      0x40000000
  43 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  44 #define CONFIG_PCI_MEM_SIZE     0x10000000
  45
  46 #define CONFIG_PCI_IO_BUS       0x50000000
  47 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  48 #define CONFIG_PCI_IO_SIZE      0x01000000
  49
  50 #define CONFIG_SYS_XLB_PIPELINING       1
  51 #define CONFIG_HIGH_BATS        1
  52
  53 #define MV_CI                   mvSMR
  54 #define MV_VCI                  mvSMR
  55 #define MV_FPGA_DATA            0xff840000
  56 #define MV_FPGA_SIZE            0x1ff88
  57 #define MV_KERNEL_ADDR          0xfff00000
  58 #define MV_SCRIPT_ADDR          0xff806000
  59 #define MV_INITRD_ADDR          0xff880000
  60 #define MV_INITRD_LENGTH        0x00240000
  61 #define MV_SCRATCH_ADDR         0xffcc0000
  62 #define MV_SCRATCH_LENGTH       MV_INITRD_LENGTH
  63
  64 #define CONFIG_SHOW_BOOT_PROGRESS 1
  65
  66 #define MV_KERNEL_ADDR_RAM      0x00100000
  67 #define MV_INITRD_ADDR_RAM      0x00400000
  68
  69 /*
  70  * Supported commands
  71  */
  72 #include <config_cmd_default.h>
  73
  74 #define CONFIG_CMD_CACHE
  75 #define CONFIG_CMD_DHCP
  76 #define CONFIG_CMD_FPGA
  77 #define CONFIG_CMD_I2C
  78 #define CONFIG_CMD_MII
  79 #define CONFIG_CMD_NET
  80 #define CONFIG_CMD_PCI
  81 #define CONFIG_CMD_PING
  82 #define CONFIG_CMD_SDRAM
  83
  84 #define CONFIG_BOOTP_BOOTFILESIZE
  85 #define CONFIG_BOOTP_BOOTPATH
  86 #define CONFIG_BOOTP_DNS
  87 #define CONFIG_BOOTP_DNS2
  88 #define CONFIG_BOOTP_GATEWAY
  89 #define CONFIG_BOOTP_HOSTNAME
  90 #define CONFIG_BOOTP_NTPSERVER
  91 #define CONFIG_BOOTP_RANDOM_DELAY
  92 #define CONFIG_BOOTP_SEND_HOSTNAME
  93 #define CONFIG_BOOTP_SUBNETMASK
  94 #define CONFIG_BOOTP_VENDOREX
  95 #define CONFIG_LIB_RAND
  96
  97 /*
  98  * Autoboot
  99  */
 100 #define CONFIG_BOOTDELAY                1
 101 #define CONFIG_AUTOBOOT_KEYED
 102 #define CONFIG_AUTOBOOT_STOP_STR        "abcdefg"
 103 #define CONFIG_ZERO_BOOTDELAY_CHECK
 104
 105 #define CONFIG_BOOTCOMMAND      "source ${script_addr}"
 106 #define CONFIG_BOOTARGS         "root=/dev/ram ro rootfstype=squashfs" \
 107                                         " allocate=6M"
 108
 109 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 110         "console_nr=0\0"                                        \
 111         "console=no\0"                                          \
 112         "stdin=serial\0"                                        \
 113         "stdout=serial\0"                                       \
 114         "stderr=serial\0"                                       \
 115         "fpga=0\0"                                              \
 116         "fpgadata=" __stringify(MV_FPGA_DATA) "\0"                      \
 117         "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"          \
 118         "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"              \
 119         "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"      \
 120         "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"         \
 121         "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"              \
 122         "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"      \
 123         "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"  \
 124         "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0"            \
 125         "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0"        \
 126         "mv_version=" U_BOOT_VERSION "\0"                       \
 127         "dhcp_client_id=" __stringify(MV_CI) "\0"                       \
 128         "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0"        \
 129         "netretry=no\0"                                         \
 130         "use_static_ipaddr=no\0"                                \
 131         "static_ipaddr=192.168.0.101\0"                         \
 132         "static_netmask=255.255.255.0\0"                        \
 133         "static_gateway=0.0.0.0\0"                              \
 134         "initrd_name=uInitrd.mvsmr-rfs\0"                       \
 135         "zcip=yes\0"                                            \
 136         "netboot=no\0"                                          \
 137         ""
 138
 139 /*
 140  * IPB Bus clocking configuration.
 141  */
 142 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
 143
 144 /*
 145  * Flash configuration
 146  */
 147 #undef  CONFIG_FLASH_16BIT
 148 #define CONFIG_SYS_FLASH_CFI
 149 #define CONFIG_FLASH_CFI_DRIVER
 150 #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
 151 #define CONFIG_SYS_FLASH_EMPTY_INFO
 152
 153 #define CONFIG_SYS_FLASH_ERASE_TOUT     50000
 154 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000
 155
 156 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 157 #define CONFIG_SYS_MAX_FLASH_SECT       256
 158
 159 #define CONFIG_SYS_LOWBOOT
 160 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_TEXT_BASE
 161 #define CONFIG_SYS_FLASH_SIZE           0x00800000
 162
 163 /*
 164  * Environment settings
 165  */
 166 #define CONFIG_ENV_IS_IN_FLASH
 167 #undef  CONFIG_SYS_FLASH_PROTECTION
 168 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 169
 170 #define CONFIG_ENV_OFFSET       0x8000
 171 #define CONFIG_ENV_SIZE         0x2000
 172 #define CONFIG_ENV_SECT_SIZE    0x2000
 173
 174 /* used by linker script to wrap code around */
 175 #define CONFIG_SCRIPT_OFFSET    0x6000
 176 #define CONFIG_SCRIPT_SECT_SIZE 0x2000
 177
 178 /*
 179  * Memory map
 180  */
 181 #define CONFIG_SYS_MBAR         0xF0000000
 182 #define CONFIG_SYS_SDRAM_BASE   0x00000000
 183 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 184
 185 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 186 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 187
 188 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 189                                                 GENERATED_GBL_DATA_SIZE)
 190 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 191
 192 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 193 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 194 #define CONFIG_SYS_RAMBOOT              1
 195 #endif
 196
 197 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 198 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)
 199 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
 200 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 201
 202 /*
 203  * I2C configuration
 204  */
 205 #define CONFIG_HARD_I2C         1
 206 #define CONFIG_SYS_I2C_MODULE   1
 207 #define CONFIG_SYS_I2C_SPEED    86000
 208 #define CONFIG_SYS_I2C_SLAVE    0x7F
 209
 210 /*
 211  * Ethernet configuration
 212  */
 213 #define CONFIG_NET_RETRY_COUNT 5
 214
 215 #define CONFIG_MPC5xxx_FEC
 216 #define CONFIG_MPC5xxx_FEC_MII100
 217 #define CONFIG_PHY_ADDR         0x00
 218 #define CONFIG_NETDEV           eth0
 219
 220 /*
 221  * Miscellaneous configurable options
 222  */
 223 #define CONFIG_SYS_HUSH_PARSER
 224 #define CONFIG_CMDLINE_EDITING
 225 #undef  CONFIG_SYS_LONGHELP
 226 #ifdef CONFIG_CMD_KGDB
 227 #define CONFIG_SYS_CBSIZE               1024
 228 #else
 229 #define CONFIG_SYS_CBSIZE               256
 230 #endif
 231 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 232 #define CONFIG_SYS_MAXARGS              16
 233 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 234
 235 #define CONFIG_SYS_MEMTEST_START        0x00800000
 236 #define CONFIG_SYS_MEMTEST_END          0x02f00000
 237
 238 /* default load address */
 239 #define CONFIG_SYS_LOAD_ADDR            0x02000000
 240 /* default location for tftp and bootm */
 241 #define CONFIG_LOADADDR                 0x00200000
 242
 243 /*
 244  * Various low-level settings
 245  */
 246 #define CONFIG_SYS_GPS_PORT_CONFIG      0x00050044
 247
 248 #define CONFIG_SYS_HID0_INIT            (HID0_ICE | HID0_ICFI)
 249 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 250
 251 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 252 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 253 #define CONFIG_SYS_BOOTCS_CFG           0x00047800
 254 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 255 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 256
 257 #define CONFIG_SYS_CS_BURST             0x000000f0
 258 #define CONFIG_SYS_CS_DEADCYCLE         0x33333303
 259
 260 #define CONFIG_SYS_RESET_ADDRESS        0x00000100
 261
 262 #undef FPGA_DEBUG
 263 #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
 264 #define CONFIG_FPGA
 265 #define CONFIG_FPGA_XILINX      1
 266 #define CONFIG_FPGA_SPARTAN2    1
 267 #define CONFIG_FPGA_COUNT       1
 268
 269 #endif