3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #define MV_VERSION "v0.2.0"
30 /* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
33 #define ERR_BOOTM_BADMAGIC 2
34 #define ERR_BOOTM_BADCRC 3
35 #define ERR_BOOTM_GUNZIP 4
36 #define ERR_BOOTP_TIMEOUT 5
42 #define CONFIG_BOARD_TYPES 1
43 #define MVBLUE_BOARD_BOX 1
44 #define MVBLUE_BOARD_LYNX 2
47 #define ERR_LED(code) do { if (code) \
48 *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
50 *(volatile char *)(0xff000003) = ( 1 ); \
58 #define CONFIG_MPC824X 1
59 #define CONFIG_MPC8245 1
60 #define CONFIG_MVBLUE 1
62 #define CONFIG_CLOCKS_IN_MHZ 1
64 #define CONFIG_BOARD_TYPES 1
66 #define CONFIG_CONS_INDEX 1
67 #define CONFIG_BAUDRATE 115200
68 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
70 #define CONFIG_BOOTDELAY 3
71 #define CONFIG_BOOT_RETRY_TIME -1
73 #define CONFIG_AUTOBOOT_KEYED
74 #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 's')...\n"
75 #define CONFIG_AUTOBOOT_STOP_STR "s"
76 #define CONFIG_ZERO_BOOTDELAY_CHECK
77 #define CONFIG_RESET_TO_RETRY 60
81 * Command line configuration.
84 #define CONFIG_CMD_ASKENV
85 #define CONFIG_CMD_BOOTD
86 #define CONFIG_CMD_CACHE
87 #define CONFIG_CMD_DHCP
88 #define CONFIG_CMD_ECHO
89 #define CONFIG_CMD_ENV
90 #define CONFIG_CMD_FLASH
91 #define CONFIG_CMD_IMI
92 #define CONFIG_CMD_IRQ
93 #define CONFIG_CMD_NET
94 #define CONFIG_CMD_PCI
95 #define CONFIG_CMD_RUN
98 #define CONFIG_BOOTP_MASK ( 0xffffffff )
101 * Miscellaneous configurable options
103 #define CFG_LONGHELP /* undef to save memory */
104 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
105 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
107 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
108 #define CFG_MAXARGS 16 /* Max number of command args */
109 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
110 #define CFG_LOAD_ADDR 0x00100000 /* Default load address */
112 #define CONFIG_BOOTCOMMAND "run nfsboot"
113 #define CONFIG_BOOTARGS "root=/dev/mtdblock5 ro rootfstype=jffs2"
115 #define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm"
117 #define CONFIG_EXTRA_ENV_SETTINGS \
119 "dhcp_client_id=mvBOX-XP\0" \
120 "dhcp_vendor-class-identifier=mvBOX\0" \
121 "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0" \
122 "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" \
123 "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" \
124 "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" \
125 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
126 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
127 "addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
128 "mv_version=" MV_VERSION "\0" \
131 #define CONFIG_OVERWRITE_ETHADDR_ONCE
133 /*-----------------------------------------------------------------------
135 *-----------------------------------------------------------------------
139 #define CONFIG_PCI_PNP
140 #define CONFIG_PCI_SCAN_SHOW
142 #define CONFIG_NET_MULTI
143 #define CONFIG_NET_RETRY_COUNT 5
146 #define CONFIG_TULIP_FIX_DAVICOM 1
147 #define CONFIG_ETHADDR b6:b4:45:eb:fb:c0
149 #define CONFIG_HW_WATCHDOG
151 /*-----------------------------------------------------------------------
152 * Start addresses for the final memory configuration
153 * (Set up by the startup code)
154 * Please note that CFG_SDRAM_BASE _must_ start at 0
156 #define CFG_SDRAM_BASE 0x00000000
158 #define CFG_FLASH_BASE 0xFFF00000
159 #define CFG_MONITOR_BASE TEXT_BASE
161 #define CFG_RESET_ADDRESS 0xFFF00100
162 #define CFG_EUMB_ADDR 0xFC000000
164 #define CFG_MONITOR_LEN 0x00100000
165 #define CFG_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */
167 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
168 #define CFG_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */
170 /* Maximum amount of RAM. */
171 #define CFG_MAX_RAM_SIZE 0x10000000 /* 0 .. 256MB of (S)DRAM */
174 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
180 #define CFG_ISA_IO 0xFE000000
183 * serial configuration
186 #define CFG_NS16550_SERIAL
188 #define CFG_NS16550_REG_SIZE 1
190 #define CFG_NS16550_CLK get_bus_freq(0)
192 #define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
193 #define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
195 /*-----------------------------------------------------------------------
196 * Definitions for initial stack pointer and data area
198 #define CFG_INIT_RAM_ADDR 0x40000000
199 #define CFG_INIT_RAM_END 0x1000
200 #define CFG_GBL_DATA_SIZE 128
201 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
204 * Low Level Configuration Settings
205 * (address mappings, register initial values, etc.)
206 * You should know what you are doing if you make changes here.
207 * For the detail description refer to the MPC8240 user's manual.
210 #define CONFIG_SYS_CLK_FREQ 33000000
213 /* Bit-field values for MCCR1. */
215 #define CFG_ROMFAL 11
217 /* Bit-field values for MCCR2. */
218 #define CFG_TSWAIT 0x5
219 #define CFG_REFINT 430
221 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
222 #define CFG_BSTOPRE 121
224 /* Bit-field values for MCCR3. */
227 /* Bit-field values for MCCR4. */
228 #define CFG_PRETOACT 3
229 #define CFG_ACTTOPRE 5
231 #define CFG_SDMODE_CAS_LAT 3
232 #define CFG_REGISTERD_TYPE_BUFFER 1
234 #define CFG_REGDIMM 0
235 #define CFG_DBUS_SIZE2 1
236 #define CFG_SDMODE_WRAP 0
238 #define CFG_PGMAX 0x32
239 #define CFG_SDRAM_DSCD 0x20
241 /* Memory bank settings.
242 * Only bits 20-29 are actually used from these vales to set the
243 * start/end addresses. The upper two bits will always be 0, and the lower
244 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
245 * address. Refer to the MPC8240 book.
248 #define CFG_BANK0_START 0x00000000
249 #define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
250 #define CFG_BANK0_ENABLE 1
251 #define CFG_BANK1_START 0x3ff00000
252 #define CFG_BANK1_END 0x3fffffff
253 #define CFG_BANK1_ENABLE 0
254 #define CFG_BANK2_START 0x3ff00000
255 #define CFG_BANK2_END 0x3fffffff
256 #define CFG_BANK2_ENABLE 0
257 #define CFG_BANK3_START 0x3ff00000
258 #define CFG_BANK3_END 0x3fffffff
259 #define CFG_BANK3_ENABLE 0
260 #define CFG_BANK4_START 0x3ff00000
261 #define CFG_BANK4_END 0x3fffffff
262 #define CFG_BANK4_ENABLE 0
263 #define CFG_BANK5_START 0x3ff00000
264 #define CFG_BANK5_END 0x3fffffff
265 #define CFG_BANK5_ENABLE 0
266 #define CFG_BANK6_START 0x3ff00000
267 #define CFG_BANK6_END 0x3fffffff
268 #define CFG_BANK6_ENABLE 0
269 #define CFG_BANK7_START 0x3ff00000
270 #define CFG_BANK7_END 0x3fffffff
271 #define CFG_BANK7_ENABLE 0
273 #define CFG_ODCR 0xff
275 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
276 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
278 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
279 #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
281 #define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
282 #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
284 #define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
285 #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
287 #define CFG_DBAT0L CFG_IBAT0L
288 #define CFG_DBAT0U CFG_IBAT0U
289 #define CFG_DBAT1L CFG_IBAT1L
290 #define CFG_DBAT1U CFG_IBAT1U
291 #define CFG_DBAT2L CFG_IBAT2L
292 #define CFG_DBAT2U CFG_IBAT2U
293 #define CFG_DBAT3L CFG_IBAT3L
294 #define CFG_DBAT3U CFG_IBAT3U
297 * For booting Linux, the board info and command line data
298 * have to be in the first 8 MB of memory, since this is
299 * the maximum mapped by the Linux kernel during initialization.
301 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
303 /*-----------------------------------------------------------------------
306 #undef CFG_FLASH_PROTECTION
307 #define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
308 #define CFG_MAX_FLASH_SECT 63 /* Max number of sectors per flash */
310 #define CFG_FLASH_ERASE_TOUT 12000
311 #define CFG_FLASH_WRITE_TOUT 1000
314 #define CFG_ENV_IS_IN_FLASH
316 #define CFG_ENV_OFFSET 0x00010000
317 #define CFG_ENV_SIZE 0x00010000
318 #define CFG_ENV_SECT_SIZE 0x00010000
320 /*-----------------------------------------------------------------------
321 * Cache Configuration
323 #define CFG_CACHELINE_SIZE 32
324 #if defined(CONFIG_CMD_KGDB)
325 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
329 * Internal Definitions
333 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
334 #define BOOTFLAG_WARM 0x02 /* Software reboot */
336 #endif /* __CONFIG_H */