2 * Copyright (C) Matrix Vision GmbH 2008
4 * Matrix Vision mvBlueLYNX-M7 configuration file
5 * based on Freescale's MPC8349ITX.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * High Level Configuration Options
36 #define CONFIG_MPC83xx 1
37 #define CONFIG_MPC834x 1
38 #define CONFIG_MPC8343 1
40 #define CONFIG_SYS_IMMR 0xE0000000
43 #define CONFIG_83XX_GENERIC_PCI
44 #define CONFIG_PCI_SKIP_HOST_BRIDGE
45 #define CONFIG_HARD_I2C
46 #define CONFIG_TSEC_ENET
47 #define CONFIG_MPC8XXX_SPI
48 #define CONFIG_HARD_SPI
49 #define MVBLM7_MMC_CS 0x04000000
52 #undef CONFIG_SOFT_I2C
54 #define CONFIG_FSL_I2C
55 #define CONFIG_I2C_MULTI_BUS
56 #define CONFIG_SYS_I2C_OFFSET 0x3000
57 #define CONFIG_SYS_I2C2_OFFSET 0x3100
59 #define CONFIG_SYS_I2C_SPEED 100000
60 #define CONFIG_SYS_I2C_SLAVE 0x7F
65 #define CONFIG_SYS_DDR_BASE 0x00000000
66 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
67 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
68 #define CONFIG_SYS_83XX_DDR_USES_CS0 1
69 #define CONFIG_SYS_MEMTEST_START (60<<20)
70 #define CONFIG_SYS_MEMTEST_END (70<<20)
72 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
73 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
75 #define CONFIG_SYS_DDR_SIZE 256
77 /* HC, 75Ohm, DDR-II, DRQ */
78 #define CONFIG_SYS_DDRCDR 0x80000001
79 /* EN, ODT_WR, 3BA, 14row, 10col */
80 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102
81 #define CONFIG_SYS_DDR_CS1_CONFIG 0x0
82 #define CONFIG_SYS_DDR_CS2_CONFIG 0x0
83 #define CONFIG_SYS_DDR_CS3_CONFIG 0x0
85 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
86 #define CONFIG_SYS_DDR_CS1_BNDS 0x0
87 #define CONFIG_SYS_DDR_CS2_BNDS 0x0
88 #define CONFIG_SYS_DDR_CS3_BNDS 0x0
90 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
92 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
93 #define CONFIG_SYS_DDR_TIMING_1 0x2625b221
94 #define CONFIG_SYS_DDR_TIMING_2 0x1f9820c7
95 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
97 /* ~MEM_EN, SREN, DDR-II, 32_BE */
98 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000
99 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
100 #define CONFIG_SYS_DDR_INTERVAL 0x04060100
102 #define CONFIG_SYS_DDR_MODE 0x078e0232
105 #define CONFIG_SYS_FLASH_CFI
106 #define CONFIG_FLASH_CFI_DRIVER
107 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
109 #define CONFIG_SYS_FLASH_BASE 0xFF800000
110 #define CONFIG_SYS_FLASH_SIZE 8
111 #define CONFIG_SYS_FLASH_SIZE_SHIFT 3
112 #define CONFIG_SYS_FLASH_EMPTY_INFO
113 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000
114 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
115 #define CONFIG_SYS_MAX_FLASH_BANKS 1
116 #define CONFIG_SYS_MAX_FLASH_SECT 256
118 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
119 #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
120 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\
121 OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
123 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
124 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
127 * U-Boot memory configuration
129 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
130 #undef CONFIG_SYS_RAMBOOT
132 #define CONFIG_SYS_INIT_RAM_LOCK
133 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
134 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
136 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
137 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
138 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
140 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
141 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
142 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
145 * Local Bus LCRR and LBCR regs
146 * LCRR: DLL bypass, Clock divider is 4
147 * External Local Bus rate is
148 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
150 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
151 #define CONFIG_SYS_LBC_LBCR 0x00000000
153 /* LB sdram refresh timer, about 6us */
154 #define CONFIG_SYS_LBC_LSRT 0x32000000
155 /* LB refresh timer prescal, 266MHz/32*/
156 #define CONFIG_SYS_LBC_MRTPR 0x20000000
161 #define CONFIG_CONS_INDEX 1
162 #undef CONFIG_SERIAL_SOFTWARE_FIFO
163 #define CONFIG_SYS_NS16550
164 #define CONFIG_SYS_NS16550_SERIAL
165 #define CONFIG_SYS_NS16550_REG_SIZE 1
166 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
168 #define CONFIG_SYS_BAUDRATE_TABLE \
169 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
171 #define CONFIG_CONSOLE ttyS0
172 #define CONFIG_BAUDRATE 115200
174 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
175 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
177 /* pass open firmware flat tree */
178 #define CONFIG_OF_LIBFDT 1
179 #define CONFIG_OF_BOARD_SETUP 1
180 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
181 #define MV_DTB_NAME "mvblm7.dtb"
186 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
187 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
188 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
189 #define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
190 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
191 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
192 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
193 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
194 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
196 #define CONFIG_NET_MULTI 1
197 #define CONFIG_NET_RETRY_COUNT 3
200 #define CONFIG_83XX_CLKIN 66666667
201 #define CONFIG_PCI_PNP
202 #define CONFIG_PCI_SCAN_SHOW
206 #define CONFIG_SYS_VSC8601_SKEWFIX
207 #define CONFIG_SYS_VSC8601_SKEW_TX 3
208 #define CONFIG_SYS_VSC8601_SKEW_RX 3
213 #define CONFIG_HAS_ETH0
214 #define CONFIG_TSEC1_NAME "TSEC0"
215 #define CONFIG_FEC1_PHY_NORXERR
216 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
217 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
218 #define TSEC1_PHY_ADDR 0x10
219 #define TSEC1_PHYIDX 0
220 #define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
222 #define CONFIG_HAS_ETH1
223 #define CONFIG_TSEC2_NAME "TSEC1"
224 #define CONFIG_FEC2_PHY_NORXERR
225 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
226 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
227 #define TSEC2_PHY_ADDR 0x11
228 #define TSEC2_PHYIDX 0
229 #define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
231 #define CONFIG_ETHPRIME "TSEC0"
233 #define CONFIG_BOOTP_VENDOREX
234 #define CONFIG_BOOTP_SUBNETMASK
235 #define CONFIG_BOOTP_GATEWAY
236 #define CONFIG_BOOTP_DNS
237 #define CONFIG_BOOTP_DNS2
238 #define CONFIG_BOOTP_HOSTNAME
239 #define CONFIG_BOOTP_BOOTFILESIZE
240 #define CONFIG_BOOTP_BOOTPATH
241 #define CONFIG_BOOTP_NTPSERVER
242 #define CONFIG_BOOTP_RANDOM_DELAY
243 #define CONFIG_BOOTP_SEND_HOSTNAME
246 #define CONFIG_HAS_FSL_DR_USB
251 #undef CONFIG_SYS_FLASH_PROTECTION
252 #define CONFIG_ENV_OVERWRITE
254 #define CONFIG_ENV_IS_IN_FLASH 1
255 #define CONFIG_ENV_ADDR 0xFF800000
256 #define CONFIG_ENV_SIZE 0x2000
257 #define CONFIG_ENV_SECT_SIZE 0x2000
258 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
259 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
261 #define CONFIG_LOADS_ECHO
262 #define CONFIG_SYS_LOADS_BAUD_CHANGE
265 * Command line configuration.
267 #include <config_cmd_default.h>
269 #define CONFIG_CMD_CACHE
270 #define CONFIG_CMD_IRQ
271 #define CONFIG_CMD_NET
272 #define CONFIG_CMD_MII
273 #define CONFIG_CMD_PING
274 #define CONFIG_CMD_DHCP
275 #define CONFIG_CMD_SDRAM
276 #define CONFIG_CMD_PCI
277 #define CONFIG_CMD_I2C
278 #define CONFIG_CMD_FPGA
280 #undef CONFIG_WATCHDOG
283 * Miscellaneous configurable options
285 #define CONFIG_SYS_LONGHELP
286 #define CONFIG_CMDLINE_EDITING
287 #define CONFIG_SYS_HUSH_PARSER
288 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
290 /* default load address */
291 #define CONFIG_SYS_LOAD_ADDR 0x2000000
292 /* default location for tftp and bootm */
293 #define CONFIG_LOADADDR 0x200000
295 #define CONFIG_SYS_PROMPT "mvBL-M7> "
296 #define CONFIG_SYS_CBSIZE 256
298 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
299 #define CONFIG_SYS_MAXARGS 16
300 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
301 #define CONFIG_SYS_HZ 1000
304 * For booting Linux, the board info and command line data
305 * have to be in the first 8 MB of memory, since this is
306 * the maximum mapped by the Linux kernel during initialization.
308 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
310 #define CONFIG_SYS_HRCW_LOW 0x0
311 #define CONFIG_SYS_HRCW_HIGH 0x0
316 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
317 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
318 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
319 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
322 #define CONFIG_SYS_SCCR_ENCCM 0
323 #define CONFIG_SYS_SCCR_USBMPHCM 0
324 #define CONFIG_SYS_SCCR_USBDRCM 2
325 #define CONFIG_SYS_SCCR_TSEC1CM 1
326 #define CONFIG_SYS_SCCR_TSEC2CM 1
328 #define CONFIG_SYS_SICRH 0x1fff8003
329 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
331 #define CONFIG_SYS_HID0_INIT 0x000000000
332 #define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT
334 #define CONFIG_SYS_HID2 HID2_HBE
335 #define CONFIG_HIGH_BATS 1
338 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
339 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
342 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
343 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
344 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
346 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
349 #define CONFIG_SYS_IBAT3L 0
350 #define CONFIG_SYS_IBAT3U 0
351 #define CONFIG_SYS_IBAT4L 0
352 #define CONFIG_SYS_IBAT4U 0
354 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
355 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \
357 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
359 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
360 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
362 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
363 #define CONFIG_SYS_IBAT7L 0
364 #define CONFIG_SYS_IBAT7U 0
366 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
367 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
368 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
369 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
370 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
371 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
372 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
373 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
374 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
375 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
376 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
377 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
378 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
379 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
380 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
381 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
384 * Internal Definitions
388 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
389 #define BOOTFLAG_WARM 0x02 /* Software reboot */
393 * Environment Configuration
395 #define CONFIG_ENV_OVERWRITE
397 #define CONFIG_NETDEV eth0
399 /* Default path and filenames */
400 #define CONFIG_BOOTDELAY 5
401 #define CONFIG_AUTOBOOT_KEYED
402 #define CONFIG_AUTOBOOT_STOP_STR "s"
403 #define CONFIG_ZERO_BOOTDELAY_CHECK
404 #define CONFIG_RESET_TO_RETRY 1000
406 #define MV_CI mvBL-M7
407 #define MV_VCI mvBL-M7
408 #define MV_FPGA_DATA 0xfff80000
409 #define MV_FPGA_SIZE 0x00076ca2
410 #define MV_KERNEL_ADDR 0xff810000
411 #define MV_INITRD_ADDR 0xffb00000
412 #define MV_SOURCE_ADDR 0xff804000
413 #define MV_SOURCE_ADDR2 0xff806000
414 #define MV_DTB_ADDR 0xff808000
415 #define MV_INITRD_LENGTH 0x00400000
417 #define CONFIG_SHOW_BOOT_PROGRESS 1
419 #define MV_KERNEL_ADDR_RAM 0x00100000
420 #define MV_DTB_ADDR_RAM 0x00600000
421 #define MV_INITRD_ADDR_RAM 0x01000000
423 #define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \
424 then source ${autoscr_addr}; \
425 else source ${autoscr_addr2}; \
427 #define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
429 #define CONFIG_EXTRA_ENV_SETTINGS \
431 "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \
436 "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
437 "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
438 "autoscr_addr=" MK_STR(MV_SOURCE_ADDR) "\0" \
439 "autoscr_addr2=" MK_STR(MV_SOURCE_ADDR2) "\0" \
440 "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
441 "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
442 "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
443 "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
444 "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
445 "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
446 "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
447 "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
448 "mv_version=" U_BOOT_VERSION "\0" \
449 "dhcp_client_id=" MK_STR(MV_CI) "\0" \
450 "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
452 "use_static_ipaddr=no\0" \
453 "static_ipaddr=192.168.90.10\0" \
454 "static_netmask=255.255.255.0\0" \
455 "static_gateway=0.0.0.0\0" \
456 "initrd_name=uInitrd.mvblm7-xenorfs\0" \
460 "tried_bootfromflash=no\0" \
461 "tried_bootfromnet=no\0" \
462 "bootfile=mvblm72625.boot\0" \
465 "mvbcdma_debug=0\0" \
467 "propdev_debug=0\0" \
470 "usb_dr_mode=host\0" \
474 #define CONFIG_FPGA_COUNT 1
475 #define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
476 #define CONFIG_FPGA_ALTERA
477 #define CONFIG_FPGA_CYCLON2