include/configs/MVBLM7.h

   1 /*
   2  * Copyright (C) Matrix Vision GmbH 2008
   3  *
   4  * Matrix Vision mvBlueLYNX-M7 configuration file
   5  * based on Freescale's MPC8349ITX.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #include <version.h>
  31
  32 /*
  33  * High Level Configuration Options
  34  */
  35 #define CONFIG_E300     1
  36 #define CONFIG_MPC83XX  1
  37 #define CONFIG_MPC834X  1
  38 #define CONFIG_MPC8343  1
  39
  40 #define CONFIG_SYS_IMMR         0xE0000000
  41
  42 #define CONFIG_PCI
  43 #define CONFIG_83XX_GENERIC_PCI
  44 #define CONFIG_PCI_SKIP_HOST_BRIDGE
  45 #define CONFIG_HARD_I2C
  46 #define CONFIG_TSEC_ENET
  47 #define CONFIG_MPC8XXX_SPI
  48 #define CONFIG_HARD_SPI
  49 #define MVBLM7_MMC_CS   0x04000000
  50
  51 /* I2C */
  52 #undef CONFIG_SOFT_I2C
  53
  54 #define CONFIG_FSL_I2C
  55 #define CONFIG_I2C_MULTI_BUS
  56 #define CONFIG_I2C_CMD_TREE
  57 #define CONFIG_SYS_I2C_OFFSET           0x3000
  58 #define CONFIG_SYS_I2C2_OFFSET          0x3100
  59
  60 #define CONFIG_SYS_I2C_SPEED            100000
  61 #define CONFIG_SYS_I2C_SLAVE            0x7F
  62
  63 /*
  64  * DDR Setup
  65  */
  66 #define CONFIG_SYS_DDR_BASE             0x00000000
  67 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  68 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  69 #define CONFIG_SYS_83XX_DDR_USES_CS0    1
  70 #define CONFIG_SYS_MEMTEST_START        (60<<20)
  71 #define CONFIG_SYS_MEMTEST_END          (70<<20)
  72
  73 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  74                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  75
  76 #define CONFIG_SYS_DDR_SIZE             256
  77
  78 /* HC, 75Ohm, DDR-II, DRQ */
  79 #define CONFIG_SYS_DDRCDR               0x80000001
  80 /* EN, ODT_WR, 3BA, 14row, 10col */
  81 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014102
  82 #define CONFIG_SYS_DDR_CS1_CONFIG       0x0
  83 #define CONFIG_SYS_DDR_CS2_CONFIG       0x0
  84 #define CONFIG_SYS_DDR_CS3_CONFIG       0x0
  85
  86 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
  87 #define CONFIG_SYS_DDR_CS1_BNDS 0x0
  88 #define CONFIG_SYS_DDR_CS2_BNDS 0x0
  89 #define CONFIG_SYS_DDR_CS3_BNDS 0x0
  90
  91 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
  92
  93 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
  94 #define CONFIG_SYS_DDR_TIMING_1 0x2625b221
  95 #define CONFIG_SYS_DDR_TIMING_2 0x1f9820c7
  96 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  97
  98 /* ~MEM_EN, SREN, DDR-II, 32_BE */
  99 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43080000
 100 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 101 #define CONFIG_SYS_DDR_INTERVAL 0x04060100
 102
 103 #define CONFIG_SYS_DDR_MODE             0x078e0232
 104
 105 /* Flash */
 106 #define CONFIG_SYS_FLASH_CFI
 107 #define CONFIG_FLASH_CFI_DRIVER
 108 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 109
 110 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 111 #define CONFIG_SYS_FLASH_SIZE           8
 112 #define CONFIG_SYS_FLASH_SIZE_SHIFT     3
 113 #define CONFIG_SYS_FLASH_EMPTY_INFO
 114 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000
 115 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
 116 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 117 #define CONFIG_SYS_MAX_FLASH_SECT       256
 118
 119 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
 120 #define CONFIG_SYS_OR0_PRELIM           ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM |  \
 121                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\
 122                                 OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
 123                                 OR_GPCM_EAD)
 124 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 125 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
 126
 127 /*
 128  * U-Boot memory configuration
 129  */
 130 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
 131 #undef  CONFIG_SYS_RAMBOOT
 132
 133 #define CONFIG_L1_INIT_RAM
 134 #define CONFIG_SYS_INIT_RAM_LOCK
 135 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM address */
 136 #define CONFIG_SYS_INIT_RAM_END 0x1000          /* End of used area in RAM*/
 137
 138 #define CONFIG_SYS_GBL_DATA_SIZE        0x100           /* num bytes initial data */
 139 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 140 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 141
 142 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 143 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 144 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 145
 146 /*
 147  * Local Bus LCRR and LBCR regs
 148  *  LCRR:  DLL bypass, Clock divider is 4
 149  * External Local Bus rate is
 150  *  CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 151  */
 152 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
 153 #define CONFIG_SYS_LBC_LBCR     0x00000000
 154
 155 /* LB sdram refresh timer, about 6us */
 156 #define CONFIG_SYS_LBC_LSRT     0x32000000
 157 /* LB refresh timer prescal, 266MHz/32*/
 158 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 159
 160 /*
 161  * Serial Port
 162  */
 163 #define CONFIG_CONS_INDEX       1
 164 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 165 #define CONFIG_SYS_NS16550
 166 #define CONFIG_SYS_NS16550_SERIAL
 167 #define CONFIG_SYS_NS16550_REG_SIZE     1
 168 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 169
 170 #define CONFIG_SYS_BAUDRATE_TABLE  \
 171         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 172
 173 #define CONFIG_CONSOLE          ttyS0
 174 #define CONFIG_BAUDRATE         115200
 175
 176 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 177 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 178
 179 /* pass open firmware flat tree */
 180 #define CONFIG_OF_LIBFDT                1
 181 #define CONFIG_OF_BOARD_SETUP           1
 182 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 183 #define MV_DTB_NAME     "mvblm7.dtb"
 184
 185 /*
 186  * PCI
 187  */
 188 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 189 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 190 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000
 191 #define CONFIG_SYS_PCI1_MMIO_BASE       (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 192 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 193 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000
 194 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 195 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 196 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
 197
 198 #define _IO_BASE                0x00000000
 199
 200 #define CONFIG_NET_MULTI        1
 201 #define CONFIG_NET_RETRY_COUNT  3
 202
 203 #define PCI_66M
 204 #define CONFIG_83XX_CLKIN       66666667
 205 #define CONFIG_PCI_PNP
 206 #define CONFIG_PCI_SCAN_SHOW
 207
 208 /* TSEC */
 209 #define CONFIG_GMII
 210 #define CONFIG_SYS_VSC8601_SKEWFIX
 211 #define CONFIG_SYS_VSC8601_SKEW_TX      3
 212 #define CONFIG_SYS_VSC8601_SKEW_RX      3
 213
 214 #define CONFIG_TSEC1
 215 #define CONFIG_TSEC2
 216
 217 #define CONFIG_HAS_ETH0
 218 #define CONFIG_TSEC1_NAME       "TSEC0"
 219 #define CONFIG_FEC1_PHY_NORXERR
 220 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 221 #define CONFIG_SYS_TSEC1                (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 222 #define TSEC1_PHY_ADDR          0x10
 223 #define TSEC1_PHYIDX            0
 224 #define TSEC1_FLAGS             (TSEC_GIGABIT|TSEC_REDUCED)
 225
 226 #define CONFIG_HAS_ETH1
 227 #define CONFIG_TSEC2_NAME       "TSEC1"
 228 #define CONFIG_FEC2_PHY_NORXERR
 229 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 230 #define CONFIG_SYS_TSEC2                (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 231 #define TSEC2_PHY_ADDR          0x11
 232 #define TSEC2_PHYIDX            0
 233 #define TSEC2_FLAGS             (TSEC_GIGABIT|TSEC_REDUCED)
 234
 235 #define CONFIG_ETHPRIME         "TSEC0"
 236
 237 #define CONFIG_BOOTP_VENDOREX
 238 #define CONFIG_BOOTP_SUBNETMASK
 239 #define CONFIG_BOOTP_GATEWAY
 240 #define CONFIG_BOOTP_DNS
 241 #define CONFIG_BOOTP_DNS2
 242 #define CONFIG_BOOTP_HOSTNAME
 243 #define CONFIG_BOOTP_BOOTFILESIZE
 244 #define CONFIG_BOOTP_BOOTPATH
 245 #define CONFIG_BOOTP_NTPSERVER
 246 #define CONFIG_BOOTP_RANDOM_DELAY
 247 #define CONFIG_BOOTP_SEND_HOSTNAME
 248
 249 /* USB */
 250 #define CONFIG_HAS_FSL_DR_USB
 251
 252 /*
 253  * Environment
 254  */
 255 #undef  CONFIG_SYS_FLASH_PROTECTION
 256 #define CONFIG_ENV_OVERWRITE
 257
 258 #define CONFIG_ENV_IS_IN_FLASH  1
 259 #define CONFIG_ENV_ADDR         0xFF800000
 260 #define CONFIG_ENV_SIZE         0x2000
 261 #define CONFIG_ENV_SECT_SIZE    0x2000
 262 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
 263 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 264
 265 #define CONFIG_LOADS_ECHO
 266 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 267
 268 /*
 269  * Command line configuration.
 270  */
 271 #include <config_cmd_default.h>
 272
 273 #define CONFIG_CMD_CACHE
 274 #define CONFIG_CMD_IRQ
 275 #define CONFIG_CMD_NET
 276 #define CONFIG_CMD_MII
 277 #define CONFIG_CMD_PING
 278 #define CONFIG_CMD_DHCP
 279 #define CONFIG_CMD_SDRAM
 280 #define CONFIG_CMD_PCI
 281 #define CONFIG_CMD_I2C
 282 #define CONFIG_CMD_FPGA
 283
 284 #undef CONFIG_WATCHDOG
 285
 286 /*
 287  * Miscellaneous configurable options
 288  */
 289 #define CONFIG_SYS_LONGHELP
 290 #define CONFIG_CMDLINE_EDITING
 291 #define CONFIG_SYS_HUSH_PARSER
 292 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 293
 294 /* default load address */
 295 #define CONFIG_SYS_LOAD_ADDR    0x2000000
 296 /* default location for tftp and bootm */
 297 #define CONFIG_LOADADDR 0x200000
 298
 299 #define CONFIG_SYS_PROMPT       "mvBL-M7> "
 300 #define CONFIG_SYS_CBSIZE       256
 301
 302 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 303 #define CONFIG_SYS_MAXARGS      16
 304 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 305 #define CONFIG_SYS_HZ           1000
 306
 307 /*
 308  * For booting Linux, the board info and command line data
 309  * have to be in the first 8 MB of memory, since this is
 310  * the maximum mapped by the Linux kernel during initialization.
 311  */
 312 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 313
 314 #define CONFIG_SYS_HRCW_LOW     0x0
 315 #define CONFIG_SYS_HRCW_HIGH    0x0
 316
 317 /*
 318  * System performance
 319  */
 320 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 321 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
 322 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 323 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 324
 325 /* clocking */
 326 #define CONFIG_SYS_SCCR_ENCCM           0
 327 #define CONFIG_SYS_SCCR_USBMPHCM        0
 328 #define CONFIG_SYS_SCCR_USBDRCM 2
 329 #define CONFIG_SYS_SCCR_TSEC1CM 1
 330 #define CONFIG_SYS_SCCR_TSEC2CM 1
 331
 332 #define CONFIG_SYS_SICRH        0x1fff8003
 333 #define CONFIG_SYS_SICRL        (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
 334
 335 #define CONFIG_SYS_HID0_INIT    0x000000000
 336 #define CONFIG_SYS_HID0_FINAL   CONFIG_SYS_HID0_INIT
 337
 338 #define CONFIG_SYS_HID2 HID2_HBE
 339 #define CONFIG_HIGH_BATS        1
 340
 341 /* DDR  */
 342 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 343 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 344
 345 /* PCI  */
 346 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 347 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 348 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
 349                                 BATL_GUARDEDSTORAGE)
 350 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 351
 352 /* no PCI2 */
 353 #define CONFIG_SYS_IBAT3L       0
 354 #define CONFIG_SYS_IBAT3U       0
 355 #define CONFIG_SYS_IBAT4L       0
 356 #define CONFIG_SYS_IBAT4U       0
 357
 358 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 359 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \
 360                                 BATL_GUARDEDSTORAGE)
 361 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 362
 363 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
 364 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
 365 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 366 #define CONFIG_SYS_IBAT7L       0
 367 #define CONFIG_SYS_IBAT7U       0
 368
 369 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 370 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 371 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 372 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 373 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 374 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 375 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 376 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 377 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 378 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 379 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 380 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 381 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 382 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 383 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 384 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 385
 386 /*
 387  * Internal Definitions
 388  *
 389  * Boot Flags
 390  */
 391 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH */
 392 #define BOOTFLAG_WARM   0x02    /* Software reboot */
 393
 394
 395 /*
 396  * Environment Configuration
 397  */
 398 #define CONFIG_ENV_OVERWRITE
 399
 400 #define CONFIG_NETDEV           eth0
 401
 402 /* Default path and filenames */
 403 #define CONFIG_BOOTDELAY                5
 404 #define CONFIG_AUTOBOOT_KEYED
 405 #define CONFIG_AUTOBOOT_STOP_STR        "s"
 406 #define CONFIG_ZERO_BOOTDELAY_CHECK
 407 #define CONFIG_RESET_TO_RETRY           1000
 408
 409 #define MV_CI                   mvBL-M7
 410 #define MV_VCI                  mvBL-M7
 411 #define MV_FPGA_DATA            0xfff80000
 412 #define MV_FPGA_SIZE            0x00076ca2
 413 #define MV_KERNEL_ADDR          0xff810000
 414 #define MV_INITRD_ADDR          0xffb00000
 415 #define MV_AUTOSCR_ADDR         0xff804000
 416 #define MV_AUTOSCR_ADDR2        0xff806000
 417 #define MV_DTB_ADDR             0xff808000
 418 #define MV_INITRD_LENGTH        0x00400000
 419
 420 #define CONFIG_SHOW_BOOT_PROGRESS 1
 421
 422 #define MV_KERNEL_ADDR_RAM      0x00100000
 423 #define MV_DTB_ADDR_RAM         0x00600000
 424 #define MV_INITRD_ADDR_RAM      0x01000000
 425
 426 #define CONFIG_BOOTCOMMAND      "if imi ${autoscr_addr}; \
 427                                         then autoscr ${autoscr_addr};  \
 428                                         else autoscr ${autoscr_addr2}; \
 429                                 fi;"
 430 #define CONFIG_BOOTARGS         "root=/dev/ram ro rootfstype=squashfs"
 431
 432 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 433         "console_nr=0\0"                                        \
 434         "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"                \
 435         "stdin=serial\0"                                        \
 436         "stdout=serial\0"                                       \
 437         "stderr=serial\0"                                       \
 438         "fpga=0\0"                                              \
 439         "fpgadata=" MK_STR(MV_FPGA_DATA) "\0"                   \
 440         "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0"               \
 441         "autoscr_addr=" MK_STR(MV_AUTOSCR_ADDR) "\0"            \
 442         "autoscr_addr2=" MK_STR(MV_AUTOSCR_ADDR2) "\0"          \
 443         "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0"           \
 444         "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0"   \
 445         "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0"           \
 446         "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0"   \
 447         "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0"       \
 448         "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0"                 \
 449         "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0"         \
 450         "dtb_name=" MK_STR(MV_DTB_NAME) "\0"                    \
 451         "mv_version=" U_BOOT_VERSION "\0"                       \
 452         "dhcp_client_id=" MK_STR(MV_CI) "\0"                    \
 453         "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0"     \
 454         "netretry=no\0"                                         \
 455         "use_static_ipaddr=no\0"                                \
 456         "static_ipaddr=192.168.90.10\0"                         \
 457         "static_netmask=255.255.255.0\0"                        \
 458         "static_gateway=0.0.0.0\0"                              \
 459         "initrd_name=uInitrd.mvblm7-xenorfs\0"                  \
 460         "zcip=no\0"                                             \
 461         "netboot=yes\0"                                         \
 462         "mvtest=Ff\0"                                           \
 463         "tried_bootfromflash=no\0"                              \
 464         "tried_bootfromnet=no\0"                                \
 465         "bootfile=mvblm72625.boot\0"                            \
 466         "use_dhcp=yes\0"                                        \
 467         "gev_start=yes\0"                                       \
 468         "mvbcdma_debug=0\0"                                     \
 469         "mvbcia_debug=0\0"                                      \
 470         "propdev_debug=0\0"                                     \
 471         "gevss_debug=0\0"                                       \
 472         "watchdog=0\0"                                          \
 473         "usb_dr_mode=host\0"                                    \
 474         "sensor_cnt=2\0"                                        \
 475         ""
 476
 477 #define CONFIG_FPGA_COUNT       1
 478 #define CONFIG_FPGA             CONFIG_SYS_ALTERA_CYCLON2
 479 #define CONFIG_FPGA_ALTERA
 480 #define CONFIG_FPGA_CYCLON2
 481
 482 #endif