include/configs/MVBLM7.h

   1 /*
   2  * Copyright (C) Matrix Vision GmbH 2008
   3  *
   4  * Matrix Vision mvBlueLYNX-M7 configuration file
   5  * based on Freescale's MPC8349ITX.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #include <version.h>
  31
  32 /*
  33  * High Level Configuration Options
  34  */
  35 #define CONFIG_E300     1
  36 #define CONFIG_MPC83xx  1
  37 #define CONFIG_MPC834x  1
  38 #define CONFIG_MPC8343  1
  39
  40 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  41
  42 #define CONFIG_SYS_IMMR         0xE0000000
  43
  44 #define CONFIG_PCI
  45 #define CONFIG_PCI_SKIP_HOST_BRIDGE
  46 #define CONFIG_HARD_I2C
  47 #define CONFIG_TSEC_ENET
  48 #define CONFIG_MPC8XXX_SPI
  49 #define CONFIG_HARD_SPI
  50 #define MVBLM7_MMC_CS   0x04000000
  51 #define CONFIG_MISC_INIT_R
  52
  53 /* I2C */
  54 #define CONFIG_FSL_I2C
  55 #define CONFIG_I2C_MULTI_BUS
  56 #define CONFIG_SYS_I2C_OFFSET           0x3000
  57 #define CONFIG_SYS_I2C2_OFFSET          0x3100
  58
  59 #define CONFIG_SYS_I2C_SPEED            100000
  60 #define CONFIG_SYS_I2C_SLAVE            0x7F
  61
  62 /*
  63  * DDR Setup
  64  */
  65 #undef  CONFIG_SPD_EEPROM
  66
  67 #define CONFIG_SYS_DDR_BASE             0x00000000
  68 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  69 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  70 #define CONFIG_SYS_83XX_DDR_USES_CS0    1
  71 #define CONFIG_SYS_MEMTEST_START        (60<<20)
  72 #define CONFIG_SYS_MEMTEST_END          (70<<20)
  73 #define CONFIG_VERY_BIG_RAM
  74
  75 #define CONFIG_SYS_DDRCDR               (DDRCDR_PZ_HIZ \
  76                                         | DDRCDR_NZ_HIZ \
  77                                         | DDRCDR_Q_DRN)
  78                                         /* 0x22000001 */
  79 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  80
  81 #define CONFIG_SYS_DDR_SIZE             512
  82
  83 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
  84
  85 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
  86
  87 #define CONFIG_SYS_DDR_TIMING_0         0x00260802
  88 #define CONFIG_SYS_DDR_TIMING_1         0x3837c322
  89 #define CONFIG_SYS_DDR_TIMING_2         0x0f9848c6
  90 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
  91
  92 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43080008
  93 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  94 #define CONFIG_SYS_DDR_INTERVAL         0x02000100
  95
  96 #define CONFIG_SYS_DDR_MODE             0x04040242
  97 #define CONFIG_SYS_DDR_MODE2            0x00800000
  98
  99 /* Flash */
 100 #define CONFIG_SYS_FLASH_CFI
 101 #define CONFIG_FLASH_CFI_DRIVER
 102 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 103
 104 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 105 #define CONFIG_SYS_FLASH_SIZE           8
 106 #define CONFIG_SYS_FLASH_EMPTY_INFO
 107 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000
 108 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
 109 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 110 #define CONFIG_SYS_MAX_FLASH_SECT       256
 111
 112 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 113                                 | BR_PS_16 \
 114                                 | BR_MS_GPCM \
 115                                 | BR_V)
 116 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 117                                 | OR_UPM_XAM \
 118                                 | OR_GPCM_CSNT \
 119                                 | OR_GPCM_ACS_DIV2 \
 120                                 | OR_GPCM_XACS \
 121                                 | OR_GPCM_SCY_15 \
 122                                 | OR_GPCM_TRLX_SET \
 123                                 | OR_GPCM_EHTR_SET \
 124                                 | OR_GPCM_EAD)
 125 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 126 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 127
 128 /*
 129  * U-Boot memory configuration
 130  */
 131 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 132 #undef  CONFIG_SYS_RAMBOOT
 133
 134 #define CONFIG_SYS_INIT_RAM_LOCK
 135 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000 /* Initial RAM address */
 136 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM*/
 137
 138 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 139                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 140 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 141
 142 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 143 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 144 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 145
 146 /*
 147  * Local Bus LCRR and LBCR regs
 148  *  LCRR:  DLL bypass, Clock divider is 4
 149  * External Local Bus rate is
 150  *  CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 151  */
 152 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 153 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 154 #define CONFIG_SYS_LBC_LBCR     0x00000000
 155
 156 /* LB sdram refresh timer, about 6us */
 157 #define CONFIG_SYS_LBC_LSRT     0x32000000
 158 /* LB refresh timer prescal, 266MHz/32*/
 159 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 160
 161 /*
 162  * Serial Port
 163  */
 164 #define CONFIG_CONS_INDEX       1
 165 #define CONFIG_SYS_NS16550
 166 #define CONFIG_SYS_NS16550_SERIAL
 167 #define CONFIG_SYS_NS16550_REG_SIZE     1
 168 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 169
 170 #define CONFIG_SYS_BAUDRATE_TABLE  \
 171                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 172
 173 #define CONFIG_CONSOLE          ttyS0
 174 #define CONFIG_BAUDRATE         115200
 175
 176 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 177 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 178
 179 /* pass open firmware flat tree */
 180 #define CONFIG_OF_LIBFDT                1
 181 #define CONFIG_OF_BOARD_SETUP           1
 182 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 183 #define MV_DTB_NAME     "mvblm7.dtb"
 184
 185 /*
 186  * PCI
 187  */
 188 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 189 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 190 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000
 191 #define CONFIG_SYS_PCI1_MMIO_BASE       \
 192                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 193 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 194 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000
 195 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 196 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 197 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
 198
 199 #define CONFIG_NET_RETRY_COUNT  3
 200
 201 #define CONFIG_PCI_66M
 202 #define CONFIG_83XX_CLKIN       66666667
 203 #define CONFIG_PCI_PNP
 204 #define CONFIG_PCI_SCAN_SHOW
 205
 206 /* TSEC */
 207 #define CONFIG_GMII
 208 #define CONFIG_SYS_VSC8601_SKEWFIX
 209 #define CONFIG_SYS_VSC8601_SKEW_TX      3
 210 #define CONFIG_SYS_VSC8601_SKEW_RX      3
 211
 212 #define CONFIG_TSEC1
 213 #define CONFIG_TSEC2
 214
 215 #define CONFIG_HAS_ETH0
 216 #define CONFIG_TSEC1_NAME       "TSEC0"
 217 #define CONFIG_FEC1_PHY_NORXERR
 218 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 219 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 220 #define TSEC1_PHY_ADDR          0x10
 221 #define TSEC1_PHYIDX            0
 222 #define TSEC1_FLAGS             (TSEC_GIGABIT|TSEC_REDUCED)
 223
 224 #define CONFIG_HAS_ETH1
 225 #define CONFIG_TSEC2_NAME       "TSEC1"
 226 #define CONFIG_FEC2_PHY_NORXERR
 227 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 228 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 229 #define TSEC2_PHY_ADDR          0x11
 230 #define TSEC2_PHYIDX            0
 231 #define TSEC2_FLAGS             (TSEC_GIGABIT|TSEC_REDUCED)
 232
 233 #define CONFIG_ETHPRIME         "TSEC0"
 234
 235 #define CONFIG_BOOTP_VENDOREX
 236 #define CONFIG_BOOTP_SUBNETMASK
 237 #define CONFIG_BOOTP_GATEWAY
 238 #define CONFIG_BOOTP_DNS
 239 #define CONFIG_BOOTP_DNS2
 240 #define CONFIG_BOOTP_HOSTNAME
 241 #define CONFIG_BOOTP_BOOTFILESIZE
 242 #define CONFIG_BOOTP_BOOTPATH
 243 #define CONFIG_BOOTP_NTPSERVER
 244 #define CONFIG_BOOTP_RANDOM_DELAY
 245 #define CONFIG_BOOTP_SEND_HOSTNAME
 246
 247 /* USB */
 248 #define CONFIG_SYS_USB_HOST
 249 #define CONFIG_USB_EHCI
 250 #define CONFIG_USB_EHCI_FSL
 251 #define CONFIG_HAS_FSL_DR_USB
 252 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 253
 254 /*
 255  * Environment
 256  */
 257 #undef  CONFIG_SYS_FLASH_PROTECTION
 258 #define CONFIG_ENV_OVERWRITE
 259
 260 #define CONFIG_ENV_IS_IN_FLASH  1
 261 #define CONFIG_ENV_ADDR         0xFF800000
 262 #define CONFIG_ENV_SIZE         0x2000
 263 #define CONFIG_ENV_SECT_SIZE    0x2000
 264 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
 265 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 266
 267 #define CONFIG_LOADS_ECHO
 268 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 269
 270 /*
 271  * Command line configuration.
 272  */
 273 #include <config_cmd_default.h>
 274
 275 #define CONFIG_CMD_CACHE
 276 #define CONFIG_CMD_IRQ
 277 #define CONFIG_CMD_NET
 278 #define CONFIG_CMD_MII
 279 #define CONFIG_CMD_PING
 280 #define CONFIG_CMD_DHCP
 281 #define CONFIG_CMD_SDRAM
 282 #define CONFIG_CMD_PCI
 283 #define CONFIG_CMD_I2C
 284 #define CONFIG_CMD_FPGA
 285 #define CONFIG_CMD_USB
 286 #define CONFIG_DOS_PARTITION
 287
 288 #undef CONFIG_WATCHDOG
 289
 290 /*
 291  * Miscellaneous configurable options
 292  */
 293 #define CONFIG_SYS_LONGHELP
 294 #define CONFIG_CMDLINE_EDITING
 295 #define CONFIG_AUTO_COMPLETE    /* add autocompletion support   */
 296 #define CONFIG_SYS_HUSH_PARSER
 297
 298 /* default load address */
 299 #define CONFIG_SYS_LOAD_ADDR    0x2000000
 300 /* default location for tftp and bootm */
 301 #define CONFIG_LOADADDR 0x200000
 302
 303 #define CONFIG_SYS_PROMPT       "mvBL-M7> "
 304 #define CONFIG_SYS_CBSIZE       256
 305
 306 #define CONFIG_SYS_PBSIZE       \
 307                         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 308 #define CONFIG_SYS_MAXARGS      16
 309 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 310 #define CONFIG_SYS_HZ           1000
 311
 312 /*
 313  * For booting Linux, the board info and command line data
 314  * have to be in the first 256 MB of memory, since this is
 315  * the maximum mapped by the Linux kernel during initialization.
 316  */
 317                                 /* Initial Memory map for Linux*/
 318 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 319
 320 #define CONFIG_SYS_HRCW_LOW     0x0
 321 #define CONFIG_SYS_HRCW_HIGH    0x0
 322
 323 /*
 324  * System performance
 325  */
 326 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 327 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 328 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 329 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 330
 331 /* clocking */
 332 #define CONFIG_SYS_SCCR_ENCCM           0
 333 #define CONFIG_SYS_SCCR_USBMPHCM        0
 334 #define CONFIG_SYS_SCCR_USBDRCM 2
 335 #define CONFIG_SYS_SCCR_TSEC1CM 1
 336 #define CONFIG_SYS_SCCR_TSEC2CM 1
 337
 338 #define CONFIG_SYS_SICRH        0x1fef0003
 339 #define CONFIG_SYS_SICRL        (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
 340
 341 #define CONFIG_SYS_HID0_INIT    0x000000000
 342 #define CONFIG_SYS_HID0_FINAL   (CONFIG_SYS_HID0_INIT | \
 343                                  HID0_ENABLE_INSTRUCTION_CACHE)
 344
 345 #define CONFIG_SYS_HID2 HID2_HBE
 346 #define CONFIG_HIGH_BATS        1
 347
 348 /* DDR  */
 349 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 350                                 | BATL_PP_RW \
 351                                 | BATL_MEMCOHERENCE)
 352 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 353                                 | BATU_BL_256M \
 354                                 | BATU_VS \
 355                                 | BATU_VP)
 356
 357 /* PCI  */
 358 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 359                                 | BATL_PP_RW \
 360                                 | BATL_MEMCOHERENCE)
 361 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 362                                 | BATU_BL_256M \
 363                                 | BATU_VS \
 364                                 | BATU_VP)
 365 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 366                                 | BATL_PP_RW \
 367                                 | BATL_CACHEINHIBIT \
 368                                 | BATL_GUARDEDSTORAGE)
 369 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 370                                 | BATU_BL_256M \
 371                                 | BATU_VS \
 372                                 | BATU_VP)
 373
 374 /* no PCI2 */
 375 #define CONFIG_SYS_IBAT3L       0
 376 #define CONFIG_SYS_IBAT3U       0
 377 #define CONFIG_SYS_IBAT4L       0
 378 #define CONFIG_SYS_IBAT4U       0
 379
 380 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 381 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 382                                 | BATL_PP_RW \
 383                                 | BATL_CACHEINHIBIT \
 384                                 | BATL_GUARDEDSTORAGE)
 385 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 386                                 | BATU_BL_256M \
 387                                 | BATU_VS \
 388                                 | BATU_VP)
 389
 390 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
 391 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 392                                 | BATL_PP_RW \
 393                                 | BATL_MEMCOHERENCE \
 394                                 | BATL_GUARDEDSTORAGE)
 395 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 396                                 | BATU_BL_256M \
 397                                 | BATU_VS \
 398                                 | BATU_VP)
 399 #define CONFIG_SYS_IBAT7L       0
 400 #define CONFIG_SYS_IBAT7U       0
 401
 402 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 403 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 404 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 405 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 406 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 407 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 408 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 409 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 410 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 411 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 412 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 413 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 414 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 415 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 416 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 417 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 418
 419 /*
 420  * Environment Configuration
 421  */
 422 #define CONFIG_ENV_OVERWRITE
 423
 424 #define CONFIG_NETDEV           eth0
 425
 426 /* Default path and filenames */
 427 #define CONFIG_BOOTDELAY                5
 428 #define CONFIG_AUTOBOOT_KEYED
 429 #define CONFIG_AUTOBOOT_STOP_STR        "s"
 430 #define CONFIG_ZERO_BOOTDELAY_CHECK
 431 #define CONFIG_RESET_TO_RETRY           1000
 432
 433 #define MV_CI                   "mvBL-M7"
 434 #define MV_VCI                  "mvBL-M7"
 435 #define MV_FPGA_DATA            0xfff40000
 436 #define MV_FPGA_SIZE            0
 437 #define MV_KERNEL_ADDR          0xff810000
 438 #define MV_INITRD_ADDR          0xffb00000
 439 #define MV_SCRIPT_ADDR          0xff804000
 440 #define MV_SCRIPT_ADDR2         0xff806000
 441 #define MV_DTB_ADDR             0xff808000
 442 #define MV_INITRD_LENGTH        0x00400000
 443
 444 #define CONFIG_SHOW_BOOT_PROGRESS 1
 445
 446 #define MV_KERNEL_ADDR_RAM      0x00100000
 447 #define MV_DTB_ADDR_RAM         0x00600000
 448 #define MV_INITRD_ADDR_RAM      0x01000000
 449
 450 #define CONFIG_BOOTCOMMAND      "if imi ${script_addr}; "               \
 451                                         "then source ${script_addr}; "  \
 452                                         "else source ${script_addr2}; " \
 453                                 "fi;"
 454 #define CONFIG_BOOTARGS         "root=/dev/ram ro rootfstype=squashfs"
 455
 456 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 457         "console_nr=0\0"                                        \
 458         "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"           \
 459         "stdin=serial\0"                                        \
 460         "stdout=serial\0"                                       \
 461         "stderr=serial\0"                                       \
 462         "fpga=0\0"                                              \
 463         "fpgadata=" __stringify(MV_FPGA_DATA) "\0"                      \
 464         "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"          \
 465         "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"         \
 466         "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0"               \
 467         "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"              \
 468         "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"      \
 469         "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"              \
 470         "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"      \
 471         "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"  \
 472         "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0"                    \
 473         "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"            \
 474         "dtb_name=" __stringify(MV_DTB_NAME) "\0"                       \
 475         "mv_version=" U_BOOT_VERSION "\0"                       \
 476         "dhcp_client_id=" MV_CI "\0"                            \
 477         "dhcp_vendor-class-identifier=" MV_VCI "\0"             \
 478         "netretry=no\0"                                         \
 479         "use_static_ipaddr=no\0"                                \
 480         "static_ipaddr=192.168.90.10\0"                         \
 481         "static_netmask=255.255.255.0\0"                        \
 482         "static_gateway=0.0.0.0\0"                              \
 483         "initrd_name=uInitrd.mvBL-M7-rfs\0"                     \
 484         "zcip=no\0"                                             \
 485         "netboot=yes\0"                                         \
 486         "mvtest=Ff\0"                                           \
 487         "tried_bootfromflash=no\0"                              \
 488         "tried_bootfromnet=no\0"                                \
 489         "bootfile=mvblm72625.boot\0"                            \
 490         "use_dhcp=yes\0"                                        \
 491         "gev_start=yes\0"                                       \
 492         "mvbcdma_debug=0\0"                                     \
 493         "mvbcia_debug=0\0"                                      \
 494         "propdev_debug=0\0"                                     \
 495         "gevss_debug=0\0"                                       \
 496         "watchdog=0\0"                                          \
 497         "usb_dr_mode=host\0"                                    \
 498         "sensor_cnt=2\0"                                        \
 499         ""
 500
 501 #define CONFIG_FPGA_COUNT       1
 502 #define CONFIG_FPGA             CONFIG_SYS_ALTERA_CYCLON2
 503 #define CONFIG_FPGA_ALTERA
 504 #define CONFIG_FPGA_CYCLON2
 505
 506 #endif