2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2004-2008
6 * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
8 * SPDX-License-Identifier: GPL-2.0+
16 #define CONFIG_MPC5200 1
18 #ifndef CONFIG_SYS_TEXT_BASE
19 #define CONFIG_SYS_TEXT_BASE 0xFF800000
22 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000
24 #define CONFIG_MISC_INIT_R 1
26 #define CONFIG_SYS_CACHELINE_SIZE 32
27 #ifdef CONFIG_CMD_KGDB
28 #define CONFIG_SYS_CACHELINE_SHIFT 5
31 #define CONFIG_PSC_CONSOLE 1
32 #define CONFIG_BAUDRATE 115200
33 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
36 #define CONFIG_PCI_PNP 1
37 #undef CONFIG_PCI_SCAN_SHOW
38 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
40 #define CONFIG_PCI_MEM_BUS 0x40000000
41 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
42 #define CONFIG_PCI_MEM_SIZE 0x10000000
44 #define CONFIG_PCI_IO_BUS 0x50000000
45 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
46 #define CONFIG_PCI_IO_SIZE 0x01000000
48 #define CONFIG_SYS_XLB_PIPELINING 1
49 #define CONFIG_HIGH_BATS 1
51 #define MV_CI mvBlueCOUGAR-P
52 #define MV_VCI mvBlueCOUGAR-P
53 #define MV_FPGA_DATA 0xff860000
54 #define MV_FPGA_SIZE 0
55 #define MV_KERNEL_ADDR 0xffd00000
56 #define MV_INITRD_ADDR 0xff900000
57 #define MV_INITRD_LENGTH 0x00400000
58 #define MV_SCRATCH_ADDR 0x00000000
59 #define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
60 #define MV_SCRIPT_ADDR 0xff840000
61 #define MV_SCRIPT_ADDR2 0xff850000
62 #define MV_DTB_ADDR 0xfffc0000
64 #define CONFIG_SHOW_BOOT_PROGRESS 1
66 #define MV_KERNEL_ADDR_RAM 0x00100000
67 #define MV_DTB_ADDR_RAM 0x00600000
68 #define MV_INITRD_ADDR_RAM 0x01000000
70 /* pass open firmware flat tree */
71 #define CONFIG_OF_LIBFDT 1
72 #define CONFIG_OF_BOARD_SETUP 1
74 #define OF_CPU "PowerPC,5200@0"
75 #define OF_SOC "soc5200@f0000000"
76 #define OF_TBCLK (bd->bi_busfreq / 4)
77 #define MV_DTB_NAME mvbc-p.dtb
78 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
83 #include <config_cmd_default.h>
85 #define CONFIG_CMD_CACHE
86 #define CONFIG_CMD_NET
87 #define CONFIG_CMD_PING
88 #define CONFIG_CMD_DHCP
89 #define CONFIG_CMD_SDRAM
90 #define CONFIG_CMD_PCI
91 #define CONFIG_CMD_FPGA
92 #define CONFIG_CMD_FPGA_LOADMK
93 #define CONFIG_CMD_I2C
95 #undef CONFIG_WATCHDOG
97 #define CONFIG_BOOTP_VENDOREX
98 #define CONFIG_BOOTP_SUBNETMASK
99 #define CONFIG_BOOTP_GATEWAY
100 #define CONFIG_BOOTP_DNS
101 #define CONFIG_BOOTP_DNS2
102 #define CONFIG_BOOTP_HOSTNAME
103 #define CONFIG_BOOTP_BOOTFILESIZE
104 #define CONFIG_BOOTP_BOOTPATH
105 #define CONFIG_BOOTP_NTPSERVER
106 #define CONFIG_BOOTP_RANDOM_DELAY
107 #define CONFIG_BOOTP_SEND_HOSTNAME
108 #define CONFIG_LIB_RAND
113 #define CONFIG_BOOTDELAY 2
114 #define CONFIG_AUTOBOOT_KEYED
115 #define CONFIG_AUTOBOOT_STOP_STR "s"
116 #define CONFIG_ZERO_BOOTDELAY_CHECK
117 #define CONFIG_RESET_TO_RETRY 1000
119 #define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
120 then source ${script_addr}; \
121 else source ${script_addr2}; \
124 #define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
125 #define CONFIG_ENV_OVERWRITE
127 #define CONFIG_EXTRA_ENV_SETTINGS \
134 "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
135 "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
136 "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
137 "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
138 "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
139 "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
140 "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
141 "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
142 "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
143 "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
144 "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
145 "dtb_name=" __stringify(MV_DTB_NAME) "\0" \
146 "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \
147 "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \
148 "mv_version=" U_BOOT_VERSION "\0" \
149 "dhcp_client_id=" __stringify(MV_CI) "\0" \
150 "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \
152 "use_static_ipaddr=no\0" \
153 "static_ipaddr=192.168.90.10\0" \
154 "static_netmask=255.255.255.0\0" \
155 "static_gateway=0.0.0.0\0" \
156 "initrd_name=uInitrd.mvbc-p-rfs\0" \
160 "tried_bootfromflash=no\0" \
161 "tried_bootfromnet=no\0" \
164 "mvbcdma_debug=0\0" \
166 "propdev_debug=0\0" \
173 * IPB Bus clocking configuration.
175 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
176 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
179 * Flash configuration
181 #undef CONFIG_FLASH_16BIT
182 #define CONFIG_SYS_FLASH_CFI
183 #define CONFIG_FLASH_CFI_DRIVER
184 #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
185 #define CONFIG_SYS_FLASH_EMPTY_INFO
187 #define CONFIG_SYS_FLASH_ERASE_TOUT 50000
188 #define CONFIG_SYS_FLASH_WRITE_TOUT 1000
190 #define CONFIG_SYS_MAX_FLASH_BANKS 1
191 #define CONFIG_SYS_MAX_FLASH_SECT 256
193 #define CONFIG_SYS_LOWBOOT
194 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
195 #define CONFIG_SYS_FLASH_SIZE 0x00800000
198 * Environment settings
200 #define CONFIG_ENV_IS_IN_FLASH
201 #undef CONFIG_SYS_FLASH_PROTECTION
203 #define CONFIG_ENV_ADDR 0xFFFE0000
204 #define CONFIG_ENV_SIZE 0x10000
205 #define CONFIG_ENV_SECT_SIZE 0x10000
206 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
207 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
212 #define CONFIG_SYS_MBAR 0xF0000000
213 #define CONFIG_SYS_SDRAM_BASE 0x00000000
214 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
216 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
217 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
219 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
220 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
222 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
223 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
224 #define CONFIG_SYS_RAMBOOT 1
227 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
228 #define CONFIG_SYS_MONITOR_LEN (512 << 10)
229 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
230 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
235 #define CONFIG_HARD_I2C 1
236 #define CONFIG_SYS_I2C_MODULE 1
237 #define CONFIG_SYS_I2C_SPEED 86000
238 #define CONFIG_SYS_I2C_SLAVE 0x7F
241 * Ethernet configuration
243 #define CONFIG_NET_RETRY_COUNT 5
246 #define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
247 #undef CONFIG_MPC5xxx_FEC
248 #undef CONFIG_PHY_ADDR
249 #define CONFIG_NETDEV eth0
252 * Miscellaneous configurable options
254 #define CONFIG_SYS_HUSH_PARSER
255 #define CONFIG_CMDLINE_EDITING
256 #undef CONFIG_SYS_LONGHELP
257 #ifdef CONFIG_CMD_KGDB
258 #define CONFIG_SYS_CBSIZE 1024
260 #define CONFIG_SYS_CBSIZE 256
262 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
263 #define CONFIG_SYS_MAXARGS 16
264 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
266 #define CONFIG_SYS_MEMTEST_START 0x00800000
267 #define CONFIG_SYS_MEMTEST_END 0x02f00000
269 /* default load address */
270 #define CONFIG_SYS_LOAD_ADDR 0x02000000
271 /* default location for tftp and bootm */
272 #define CONFIG_LOADADDR 0x00200000
275 * Various low-level settings
277 #define CONFIG_SYS_GPS_PORT_CONFIG 0x20000004
279 #define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
280 #define CONFIG_SYS_HID0_FINAL HID0_ICE
282 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
283 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
284 #define CONFIG_SYS_BOOTCS_CFG 0x00047800
285 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
286 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
288 #define CONFIG_SYS_CS_BURST 0x000000f0
289 #define CONFIG_SYS_CS_DEADCYCLE 0x33333303
291 #define CONFIG_SYS_RESET_ADDRESS 0x00000100
294 #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
296 #define CONFIG_FPGA_ALTERA 1
297 #define CONFIG_FPGA_CYCLON2 1
298 #define CONFIG_FPGA_COUNT 1