include/configs/MPC8641HPCN.h

   1 /*
   2  * Copyright 2006, 2010-2011 Freescale Semiconductor.
   3  *
   4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * MPC8641HPCN board configuration file
  11  *
  12  * Make sure you change the MAC address and other network params first,
  13  * search for CONFIG_SERVERIP, etc. in this file.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /* High Level Configuration Options */
  20 #define CONFIG_MP               1       /* support multiple processors */
  21 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  22 #define CONFIG_ADDR_MAP         1       /* Use addr map */
  23
  24 /*
  25  * default CCSRBAR is at 0xff700000
  26  * assume U-Boot is less than 0.5MB
  27  */
  28 #define CONFIG_SYS_TEXT_BASE    0xeff00000
  29
  30 #ifdef RUN_DIAG
  31 #define CONFIG_SYS_DIAG_ADDR         CONFIG_SYS_FLASH_BASE
  32 #endif
  33
  34 /*
  35  * virtual address to be used for temporary mappings.  There
  36  * should be 128k free at this VA.
  37  */
  38 #define CONFIG_SYS_SCRATCH_VA   0xe0000000
  39
  40 #define CONFIG_SYS_SRIO
  41 #define CONFIG_SRIO1                    /* SRIO port 1 */
  42
  43 #define CONFIG_PCIE1            1       /* PCIE controller 1 (ULI bridge) */
  44 #define CONFIG_PCIE2            1       /* PCIE controller 2 (slot) */
  45 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  46 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  47
  48 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  49 #define CONFIG_ENV_OVERWRITE
  50
  51 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  52 #define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
  53 #define CONFIG_SYS_NUM_ADDR_MAP 8       /* Number of addr map slots = 8 dbats */
  54
  55 #define CONFIG_ALTIVEC          1
  56
  57 /*
  58  * L2CR setup -- make sure this is right for your board!
  59  */
  60 #define CONFIG_SYS_L2
  61 #define L2_INIT         0
  62 #define L2_ENABLE       (L2CR_L2E)
  63
  64 #ifndef CONFIG_SYS_CLK_FREQ
  65 #ifndef __ASSEMBLY__
  66 extern unsigned long get_board_sys_clk(unsigned long dummy);
  67 #endif
  68 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  69 #endif
  70
  71 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  72 #define CONFIG_SYS_MEMTEST_END          0x00400000
  73
  74 /*
  75  * With the exception of PCI Memory and Rapid IO, most devices will simply
  76  * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
  77  * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
  78  */
  79 #ifdef CONFIG_PHYS_64BIT
  80 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
  81 #else
  82 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
  83 #endif
  84
  85 /*
  86  * Base addresses -- Note these are effective addresses where the
  87  * actual resources get mapped (not physical addresses)
  88  */
  89 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
  90 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  91
  92 /* Physical addresses */
  93 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  94 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    CONFIG_SYS_PHYS_ADDR_HIGH
  95 #define CONFIG_SYS_CCSRBAR_PHYS \
  96         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
  97                             CONFIG_SYS_CCSRBAR_PHYS_HIGH)
  98
  99 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
 100
 101 /*
 102  * DDR Setup
 103  */
 104 #undef CONFIG_FSL_DDR_INTERACTIVE
 105 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 106 #define CONFIG_DDR_SPD
 107
 108 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 109 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 110
 111 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 112 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 113 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
 114 #define CONFIG_VERY_BIG_RAM
 115
 116 #define CONFIG_NUM_DDR_CONTROLLERS      2
 117 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 118 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 119
 120 /*
 121  * I2C addresses of SPD EEPROMs
 122  */
 123 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 124 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 0 DIMM 1 */
 125 #define SPD_EEPROM_ADDRESS3     0x53    /* CTLR 1 DIMM 0 */
 126 #define SPD_EEPROM_ADDRESS4     0x54    /* CTLR 1 DIMM 1 */
 127
 128 /*
 129  * These are used when DDR doesn't use SPD.
 130  */
 131 #define CONFIG_SYS_SDRAM_SIZE           256             /* DDR is 256MB */
 132 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
 133 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102      /* Enable, no interleaving */
 134 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 135 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 136 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
 137 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 138 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 139 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 140 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
 141 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 142 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 143 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 144 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 145 #define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 146 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
 147
 148 #define CONFIG_ID_EEPROM
 149 #define CONFIG_SYS_I2C_EEPROM_NXID
 150 #define CONFIG_ID_EEPROM
 151 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 152 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 153
 154 #define CONFIG_SYS_FLASH_BASE           0xef800000     /* start of FLASH 8M */
 155 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW  CONFIG_SYS_FLASH_BASE
 156 #define CONFIG_SYS_FLASH_BASE_PHYS \
 157         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 158                             CONFIG_SYS_PHYS_ADDR_HIGH)
 159
 160 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
 161
 162 #define CONFIG_SYS_BR0_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 163                                  | 0x00001001)  /* port size 16bit */
 164 #define CONFIG_SYS_OR0_PRELIM   0xff806ff7      /* 8MB Boot Flash area*/
 165
 166 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(CF_BASE_PHYS)             \
 167                                  | 0x00001001)  /* port size 16bit */
 168 #define CONFIG_SYS_OR2_PRELIM   0xffffeff7      /* 32k Compact Flash */
 169
 170 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS)  \
 171                                  | 0x00000801) /* port size 8bit */
 172 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32k PIXIS area*/
 173
 174 /*
 175  * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
 176  * The PIXIS and CF by themselves aren't large enough to take up the 128k
 177  * required for the smallest BAT mapping, so there's a 64k hole.
 178  */
 179 #define CONFIG_SYS_LBC_BASE             0xffde0000
 180 #define CONFIG_SYS_LBC_BASE_PHYS_LOW    CONFIG_SYS_LBC_BASE
 181
 182 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 183 #define PIXIS_BASE              (CONFIG_SYS_LBC_BASE + 0x00010000)
 184 #define PIXIS_BASE_PHYS_LOW     (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
 185 #define PIXIS_BASE_PHYS         PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
 186                                                     CONFIG_SYS_PHYS_ADDR_HIGH)
 187 #define PIXIS_SIZE              0x00008000      /* 32k */
 188 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 189 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 190 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 191 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 192 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch register */
 193 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 194 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 195 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 196 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 197 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 198 #define PIXIS_VBOOT_FMAP        0x80    /* VBOOT - CFG_FLASHMAP */
 199 #define PIXIS_VBOOT_FBANK       0x40    /* VBOOT - CFG_FLASHBANK */
 200 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 201 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 202 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 203 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 204 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x40    /* Reset altbank mask*/
 205
 206 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
 207 #define CF_BASE                 (PIXIS_BASE + PIXIS_SIZE)
 208 #define CF_BASE_PHYS            (PIXIS_BASE_PHYS + PIXIS_SIZE)
 209
 210 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 211 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 212
 213 #undef  CONFIG_SYS_FLASH_CHECKSUM
 214 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 215 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 216 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 217 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 218
 219 #define CONFIG_FLASH_CFI_DRIVER
 220 #define CONFIG_SYS_FLASH_CFI
 221 #define CONFIG_SYS_FLASH_EMPTY_INFO
 222
 223 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 224 #define CONFIG_SYS_RAMBOOT
 225 #else
 226 #undef  CONFIG_SYS_RAMBOOT
 227 #endif
 228
 229 #if defined(CONFIG_SYS_RAMBOOT)
 230 #undef CONFIG_SPD_EEPROM
 231 #define CONFIG_SYS_SDRAM_SIZE   256
 232 #endif
 233
 234 #undef CONFIG_CLOCKS_IN_MHZ
 235
 236 #define CONFIG_SYS_INIT_RAM_LOCK        1
 237 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 238 #define CONFIG_SYS_INIT_RAM_ADDR        0x0fd00000      /* Initial RAM address */
 239 #else
 240 #define CONFIG_SYS_INIT_RAM_ADDR        0xf8400000      /* Initial RAM address */
 241 #endif
 242 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 243
 244 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 245 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 246
 247 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Mon */
 248 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)    /* Reserved for malloc */
 249
 250 /* Serial Port */
 251 #define CONFIG_CONS_INDEX     1
 252 #define CONFIG_SYS_NS16550_SERIAL
 253 #define CONFIG_SYS_NS16550_REG_SIZE     1
 254 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 255
 256 #define CONFIG_SYS_BAUDRATE_TABLE  \
 257         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 258
 259 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 260 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 261
 262 /*
 263  * I2C
 264  */
 265 #define CONFIG_SYS_I2C
 266 #define CONFIG_SYS_I2C_FSL
 267 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 268 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 269 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3100
 270 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 271
 272 /*
 273  * RapidIO MMU
 274  */
 275 #define CONFIG_SYS_SRIO1_MEM_BASE       0x80000000      /* base address */
 276 #ifdef CONFIG_PHYS_64BIT
 277 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW   0x00000000
 278 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x0000000c
 279 #else
 280 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW   CONFIG_SYS_SRIO1_MEM_BASE
 281 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x00000000
 282 #endif
 283 #define CONFIG_SYS_SRIO1_MEM_PHYS \
 284         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 285                             CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
 286 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 128M */
 287
 288 /*
 289  * General PCI
 290  * Addresses are mapped 1-1.
 291  */
 292
 293 #define CONFIG_SYS_PCIE1_NAME           "ULI"
 294 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 295 #ifdef CONFIG_PHYS_64BIT
 296 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 297 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW   0x00000000
 298 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH  0x0000000c
 299 #else
 300 #define CONFIG_SYS_PCIE1_MEM_BUS        CONFIG_SYS_PCIE1_MEM_VIRT
 301 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW   CONFIG_SYS_PCIE1_MEM_VIRT
 302 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH  0x00000000
 303 #endif
 304 #define CONFIG_SYS_PCIE1_MEM_PHYS \
 305         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 306                             CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
 307 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 308 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 309 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 310 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW    CONFIG_SYS_PCIE1_IO_VIRT
 311 #define CONFIG_SYS_PCIE1_IO_PHYS \
 312         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 313                             CONFIG_SYS_PHYS_ADDR_HIGH)
 314 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64K */
 315
 316 #ifdef CONFIG_PHYS_64BIT
 317 /*
 318  * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
 319  * This will increase the amount of PCI address space available for
 320  * for mapping RAM.
 321  */
 322 #define CONFIG_SYS_PCIE2_MEM_BUS        CONFIG_SYS_PCIE1_MEM_BUS
 323 #else
 324 #define CONFIG_SYS_PCIE2_MEM_BUS        (CONFIG_SYS_PCIE1_MEM_BUS \
 325                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 326 #endif
 327 #define CONFIG_SYS_PCIE2_MEM_VIRT       (CONFIG_SYS_PCIE1_MEM_VIRT \
 328                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 329 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW   (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
 330                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 331 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH  CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
 332 #define CONFIG_SYS_PCIE2_MEM_PHYS       (CONFIG_SYS_PCIE1_MEM_PHYS \
 333                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 334 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 335 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 336 #define CONFIG_SYS_PCIE2_IO_VIRT        (CONFIG_SYS_PCIE1_IO_VIRT \
 337                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 338 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW    (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
 339                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 340 #define CONFIG_SYS_PCIE2_IO_PHYS        (CONFIG_SYS_PCIE1_IO_PHYS \
 341                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 342 #define CONFIG_SYS_PCIE2_IO_SIZE        CONFIG_SYS_PCIE1_IO_SIZE
 343
 344 #if defined(CONFIG_PCI)
 345
 346 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 347
 348 #undef CONFIG_EEPRO100
 349 #undef CONFIG_TULIP
 350
 351 /************************************************************
 352  * USB support
 353  ************************************************************/
 354 #define CONFIG_PCI_OHCI                 1
 355 #define CONFIG_USB_OHCI_NEW             1
 356 #define CONFIG_SYS_USB_EVENT_POLL               1
 357 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
 358 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 359 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 360
 361 /*PCIE video card used*/
 362 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE2_IO_VIRT
 363
 364 /*PCI video card used*/
 365 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCIE1_IO_VIRT*/
 366
 367 /* video */
 368
 369 #if defined(CONFIG_VIDEO)
 370 #define CONFIG_BIOSEMU
 371 #define CONFIG_ATI_RADEON_FB
 372 #define CONFIG_VIDEO_LOGO
 373 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
 374 #endif
 375
 376 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 377
 378 #define CONFIG_DOS_PARTITION
 379 #define CONFIG_SCSI_AHCI
 380
 381 #ifdef CONFIG_SCSI_AHCI
 382 #define CONFIG_LIBATA
 383 #define CONFIG_SATA_ULI5288
 384 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 385 #define CONFIG_SYS_SCSI_MAX_LUN 1
 386 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 387 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 388 #endif
 389
 390 #endif  /* CONFIG_PCI */
 391
 392 #if defined(CONFIG_TSEC_ENET)
 393
 394 #define CONFIG_MII              1       /* MII PHY management */
 395
 396 #define CONFIG_TSEC1            1
 397 #define CONFIG_TSEC1_NAME       "eTSEC1"
 398 #define CONFIG_TSEC2            1
 399 #define CONFIG_TSEC2_NAME       "eTSEC2"
 400 #define CONFIG_TSEC3            1
 401 #define CONFIG_TSEC3_NAME       "eTSEC3"
 402 #define CONFIG_TSEC4            1
 403 #define CONFIG_TSEC4_NAME       "eTSEC4"
 404
 405 #define TSEC1_PHY_ADDR          0
 406 #define TSEC2_PHY_ADDR          1
 407 #define TSEC3_PHY_ADDR          2
 408 #define TSEC4_PHY_ADDR          3
 409 #define TSEC1_PHYIDX            0
 410 #define TSEC2_PHYIDX            0
 411 #define TSEC3_PHYIDX            0
 412 #define TSEC4_PHYIDX            0
 413 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 414 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 415 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 416 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 417
 418 #define CONFIG_ETHPRIME         "eTSEC1"
 419
 420 #endif  /* CONFIG_TSEC_ENET */
 421
 422 #ifdef CONFIG_PHYS_64BIT
 423 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
 424 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
 425
 426 /* Put physical address into the BAT format */
 427 #define BAT_PHYS_ADDR(low, high) \
 428         (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
 429 /* Convert high/low pairs to actual 64-bit value */
 430 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
 431 #else
 432 /* 32-bit systems just ignore the "high" bits */
 433 #define BAT_PHYS_ADDR(low, high)        (low)
 434 #define PAIRED_PHYS_TO_PHYS(low, high)  (low)
 435 #endif
 436
 437 /*
 438  * BAT0         DDR
 439  */
 440 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 441 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 442
 443 /*
 444  * BAT1         LBC (PIXIS/CF)
 445  */
 446 #define CONFIG_SYS_DBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
 447                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 448                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 449                                  BATL_GUARDEDSTORAGE)
 450 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
 451                                  | BATU_VS | BATU_VP)
 452 #define CONFIG_SYS_IBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
 453                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 454                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 455 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 456
 457 /* if CONFIG_PCI:
 458  * BAT2         PCIE1 and PCIE1 MEM
 459  * if CONFIG_RIO
 460  * BAT2         Rapidio Memory
 461  */
 462 #ifdef CONFIG_PCI
 463 #define CONFIG_PCI_INDIRECT_BRIDGE
 464 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 465                                                CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
 466                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 467                                  | BATL_GUARDEDSTORAGE)
 468 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
 469                                  | BATU_VS | BATU_VP)
 470 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 471                                                CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
 472                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 473 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 474 #else /* CONFIG_RIO */
 475 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 476                                                CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
 477                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 478                                  BATL_GUARDEDSTORAGE)
 479 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
 480                                  | BATU_VS | BATU_VP)
 481 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 482                                                CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
 483                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 484 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 485 #endif
 486
 487 /*
 488  * BAT3         CCSR Space
 489  */
 490 #define CONFIG_SYS_DBAT3L       (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
 491                                                CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 492                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 493                                  | BATL_GUARDEDSTORAGE)
 494 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
 495                                  | BATU_VP)
 496 #define CONFIG_SYS_IBAT3L       (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
 497                                                CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 498                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 499 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 500
 501 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 502 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 503                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 504                                        | BATL_GUARDEDSTORAGE)
 505 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 506                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 507 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 508                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 509 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 510 #endif
 511
 512 /*
 513  * BAT4         PCIE1_IO and PCIE2_IO
 514  */
 515 #define CONFIG_SYS_DBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 516                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 517                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 518                                  | BATL_GUARDEDSTORAGE)
 519 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
 520                                  | BATU_VS | BATU_VP)
 521 #define CONFIG_SYS_IBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 522                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 523                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 524 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 525
 526 /*
 527  * BAT5         Init RAM for stack in the CPU DCache (no backing memory)
 528  */
 529 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 530 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 531 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 532 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 533
 534 /*
 535  * BAT6         FLASH
 536  */
 537 #define CONFIG_SYS_DBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 538                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 539                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 540                                  | BATL_GUARDEDSTORAGE)
 541 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
 542                                  | BATU_VP)
 543 #define CONFIG_SYS_IBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 544                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 545                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 546 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 547
 548 /* Map the last 1M of flash where we're running from reset */
 549 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 550                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 551 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 552 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 553                                  | BATL_MEMCOHERENCE)
 554 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 555
 556 /*
 557  * BAT7         FREE - used later for tmp mappings
 558  */
 559 #define CONFIG_SYS_DBAT7L 0x00000000
 560 #define CONFIG_SYS_DBAT7U 0x00000000
 561 #define CONFIG_SYS_IBAT7L 0x00000000
 562 #define CONFIG_SYS_IBAT7U 0x00000000
 563
 564 /*
 565  * Environment
 566  */
 567 #ifndef CONFIG_SYS_RAMBOOT
 568     #define CONFIG_ENV_IS_IN_FLASH      1
 569     #define CONFIG_ENV_ADDR             \
 570                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 571     #define CONFIG_ENV_SECT_SIZE                0x10000 /* 64K(one sector) for env */
 572 #else
 573     #define CONFIG_ENV_IS_NOWHERE       1       /* Store ENV in memory only */
 574     #define CONFIG_ENV_ADDR             (CONFIG_SYS_MONITOR_BASE - 0x1000)
 575 #endif
 576 #define CONFIG_ENV_SIZE         0x2000
 577
 578 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 579 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 580
 581 /*
 582  * BOOTP options
 583  */
 584 #define CONFIG_BOOTP_BOOTFILESIZE
 585 #define CONFIG_BOOTP_BOOTPATH
 586 #define CONFIG_BOOTP_GATEWAY
 587 #define CONFIG_BOOTP_HOSTNAME
 588
 589 /*
 590  * Command line configuration.
 591  */
 592 #define CONFIG_CMD_REGINFO
 593
 594 #if defined(CONFIG_PCI)
 595     #define CONFIG_CMD_PCI
 596     #define CONFIG_SCSI
 597 #endif
 598
 599 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 600
 601 /*
 602  * Miscellaneous configurable options
 603  */
 604 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 605 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 606 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 607
 608 #if defined(CONFIG_CMD_KGDB)
 609     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 610 #else
 611     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 612 #endif
 613
 614 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 615 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 616 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 617
 618 /*
 619  * For booting Linux, the board info and command line data
 620  * have to be in the first 8 MB of memory, since this is
 621  * the maximum mapped by the Linux kernel during initialization.
 622  */
 623 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 624 #define CONFIG_SYS_BOOTM_LEN    (256 << 20)     /* Increase max gunzip size */
 625
 626 #if defined(CONFIG_CMD_KGDB)
 627     #define CONFIG_KGDB_BAUDRATE        230400  /* speed to run kgdb serial port */
 628 #endif
 629
 630 /*
 631  * Environment Configuration
 632  */
 633
 634 #define CONFIG_HAS_ETH0         1
 635 #define CONFIG_HAS_ETH1         1
 636 #define CONFIG_HAS_ETH2         1
 637 #define CONFIG_HAS_ETH3         1
 638
 639 #define CONFIG_IPADDR           192.168.1.100
 640
 641 #define CONFIG_HOSTNAME         unknown
 642 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 643 #define CONFIG_BOOTFILE         "uImage"
 644 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 645
 646 #define CONFIG_SERVERIP         192.168.1.1
 647 #define CONFIG_GATEWAYIP        192.168.1.1
 648 #define CONFIG_NETMASK          255.255.255.0
 649
 650 /* default location for tftp and bootm */
 651 #define CONFIG_LOADADDR         0x10000000
 652
 653 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 654
 655 #define CONFIG_BAUDRATE 115200
 656
 657 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 658         "netdev=eth0\0"                                                 \
 659         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 660         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 661                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 662                         " +$filesize; " \
 663                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 664                         " +$filesize; " \
 665                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 666                         " $filesize; "  \
 667                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 668                         " +$filesize; " \
 669                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 670                         " $filesize\0"  \
 671         "consoledev=ttyS0\0"                                            \
 672         "ramdiskaddr=0x18000000\0"                                              \
 673         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 674         "fdtaddr=0x17c00000\0"                                          \
 675         "fdtfile=mpc8641_hpcn.dtb\0"                                    \
 676         "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"                        \
 677         "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
 678         "maxcpus=2"
 679
 680 #define CONFIG_NFSBOOTCOMMAND                                           \
 681         "setenv bootargs root=/dev/nfs rw "                             \
 682               "nfsroot=$serverip:$rootpath "                            \
 683               "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 684               "console=$consoledev,$baudrate $othbootargs;"             \
 685         "tftp $loadaddr $bootfile;"                                     \
 686         "tftp $fdtaddr $fdtfile;"                                       \
 687         "bootm $loadaddr - $fdtaddr"
 688
 689 #define CONFIG_RAMBOOTCOMMAND                                           \
 690         "setenv bootargs root=/dev/ram rw "                             \
 691               "console=$consoledev,$baudrate $othbootargs;"             \
 692         "tftp $ramdiskaddr $ramdiskfile;"                               \
 693         "tftp $loadaddr $bootfile;"                                     \
 694         "tftp $fdtaddr $fdtfile;"                                       \
 695         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 696
 697 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 698
 699 #endif  /* __CONFIG_H */