1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2006, 2010-2011 Freescale Semiconductor.
5 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
9 * MPC8641HPCN board configuration file
11 * Make sure you change the MAC address and other network params first,
12 * search for CONFIG_SERVERIP, etc. in this file.
18 #include <linux/stringify.h>
20 /* High Level Configuration Options */
21 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
22 #define CONFIG_ADDR_MAP 1 /* Use addr map */
25 * default CCSRBAR is at 0xff700000
26 * assume U-Boot is less than 0.5MB
30 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
34 * virtual address to be used for temporary mappings. There
35 * should be 128k free at this VA.
37 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
39 #define CONFIG_SYS_SRIO
40 #define CONFIG_SRIO1 /* SRIO port 1 */
42 #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */
43 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */
44 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
45 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
47 #define CONFIG_ENV_OVERWRITE
49 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
50 #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
52 #define CONFIG_ALTIVEC 1
55 * L2CR setup -- make sure this is right for your board!
59 #define L2_ENABLE (L2CR_L2E)
61 #ifndef CONFIG_SYS_CLK_FREQ
63 extern unsigned long get_board_sys_clk(unsigned long dummy);
65 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
69 * With the exception of PCI Memory and Rapid IO, most devices will simply
70 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
71 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
73 #ifdef CONFIG_PHYS_64BIT
74 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
76 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
80 * Base addresses -- Note these are effective addresses where the
81 * actual resources get mapped (not physical addresses)
83 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
84 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
86 /* Physical addresses */
87 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
88 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH
89 #define CONFIG_SYS_CCSRBAR_PHYS \
90 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
91 CONFIG_SYS_CCSRBAR_PHYS_HIGH)
93 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
98 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
99 #define CONFIG_DDR_SPD
101 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
102 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
105 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
106 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
107 #define CONFIG_VERY_BIG_RAM
109 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
110 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
113 * I2C addresses of SPD EEPROMs
115 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
116 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
117 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
118 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
121 * These are used when DDR doesn't use SPD.
123 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
124 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
125 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
126 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
127 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
128 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
129 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
130 #define CONFIG_SYS_DDR_MODE_1 0x00480432
131 #define CONFIG_SYS_DDR_MODE_2 0x00000000
132 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
133 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
134 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
135 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
136 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
137 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
138 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
140 #define CONFIG_ID_EEPROM
141 #define CONFIG_SYS_I2C_EEPROM_NXID
142 #define CONFIG_ID_EEPROM
143 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
144 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
146 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
147 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE
148 #define CONFIG_SYS_FLASH_BASE_PHYS \
149 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
150 CONFIG_SYS_PHYS_ADDR_HIGH)
152 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
154 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
155 | 0x00001001) /* port size 16bit */
156 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
158 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
159 | 0x00001001) /* port size 16bit */
160 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
162 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
163 | 0x00000801) /* port size 8bit */
164 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
167 * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
168 * The PIXIS and CF by themselves aren't large enough to take up the 128k
169 * required for the smallest BAT mapping, so there's a 64k hole.
171 #define CONFIG_SYS_LBC_BASE 0xffde0000
172 #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE
174 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
175 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
176 #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
177 #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
178 CONFIG_SYS_PHYS_ADDR_HIGH)
179 #define PIXIS_SIZE 0x00008000 /* 32k */
180 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
181 #define PIXIS_VER 0x1 /* Board version at offset 1 */
182 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
183 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
184 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
185 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
186 #define PIXIS_VCTL 0x10 /* VELA Control Register */
187 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
188 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
189 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
190 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
191 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
192 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
193 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
194 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
195 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
196 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
198 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
199 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
200 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
202 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
203 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
205 #undef CONFIG_SYS_FLASH_CHECKSUM
206 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
207 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
208 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
209 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
211 #define CONFIG_SYS_FLASH_EMPTY_INFO
213 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
214 #define CONFIG_SYS_RAMBOOT
216 #undef CONFIG_SYS_RAMBOOT
219 #if defined(CONFIG_SYS_RAMBOOT)
220 #undef CONFIG_SPD_EEPROM
221 #define CONFIG_SYS_SDRAM_SIZE 256
224 #undef CONFIG_CLOCKS_IN_MHZ
226 #define CONFIG_SYS_INIT_RAM_LOCK 1
227 #ifndef CONFIG_SYS_INIT_RAM_LOCK
228 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
230 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
232 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
234 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
235 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
237 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
238 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
241 #define CONFIG_SYS_NS16550_SERIAL
242 #define CONFIG_SYS_NS16550_REG_SIZE 1
243 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
245 #define CONFIG_SYS_BAUDRATE_TABLE \
246 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
248 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
249 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
254 #define CONFIG_SYS_I2C
255 #define CONFIG_SYS_I2C_FSL
256 #define CONFIG_SYS_FSL_I2C_SPEED 400000
257 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
258 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
259 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
264 #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */
265 #ifdef CONFIG_PHYS_64BIT
266 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000
267 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c
269 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE
270 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000
272 #define CONFIG_SYS_SRIO1_MEM_PHYS \
273 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
274 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
275 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
279 * Addresses are mapped 1-1.
282 #define CONFIG_SYS_PCIE1_NAME "ULI"
283 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
284 #ifdef CONFIG_PHYS_64BIT
285 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
286 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000
287 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
289 #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
290 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT
291 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
293 #define CONFIG_SYS_PCIE1_MEM_PHYS \
294 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
295 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
296 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
297 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
298 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
299 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT
300 #define CONFIG_SYS_PCIE1_IO_PHYS \
301 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
302 CONFIG_SYS_PHYS_ADDR_HIGH)
303 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
305 #ifdef CONFIG_PHYS_64BIT
307 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
308 * This will increase the amount of PCI address space available for
311 #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS
313 #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \
314 + CONFIG_SYS_PCIE1_MEM_SIZE)
316 #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \
317 + CONFIG_SYS_PCIE1_MEM_SIZE)
318 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
319 + CONFIG_SYS_PCIE1_MEM_SIZE)
320 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
321 #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \
322 + CONFIG_SYS_PCIE1_MEM_SIZE)
323 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
324 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
325 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \
326 + CONFIG_SYS_PCIE1_IO_SIZE)
327 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
328 + CONFIG_SYS_PCIE1_IO_SIZE)
329 #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \
330 + CONFIG_SYS_PCIE1_IO_SIZE)
331 #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE
333 #if defined(CONFIG_PCI)
335 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
337 #undef CONFIG_EEPRO100
340 /************************************************************
342 ************************************************************/
343 #define CONFIG_PCI_OHCI 1
344 #define CONFIG_USB_OHCI_NEW 1
345 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
346 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
347 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
349 /*PCIE video card used*/
350 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
352 /*PCI video card used*/
353 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/
357 #if defined(CONFIG_VIDEO)
358 #define CONFIG_BIOSEMU
359 #define CONFIG_ATI_RADEON_FB
360 #define CONFIG_VIDEO_LOGO
361 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
364 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
366 #ifdef CONFIG_SCSI_AHCI
367 #define CONFIG_SATA_ULI5288
368 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
369 #define CONFIG_SYS_SCSI_MAX_LUN 1
370 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
373 #endif /* CONFIG_PCI */
375 #if defined(CONFIG_TSEC_ENET)
376 #define CONFIG_TSEC1 1
377 #define CONFIG_TSEC1_NAME "eTSEC1"
378 #define CONFIG_TSEC2 1
379 #define CONFIG_TSEC2_NAME "eTSEC2"
380 #define CONFIG_TSEC3 1
381 #define CONFIG_TSEC3_NAME "eTSEC3"
382 #define CONFIG_TSEC4 1
383 #define CONFIG_TSEC4_NAME "eTSEC4"
385 #define TSEC1_PHY_ADDR 0
386 #define TSEC2_PHY_ADDR 1
387 #define TSEC3_PHY_ADDR 2
388 #define TSEC4_PHY_ADDR 3
389 #define TSEC1_PHYIDX 0
390 #define TSEC2_PHYIDX 0
391 #define TSEC3_PHYIDX 0
392 #define TSEC4_PHYIDX 0
393 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
394 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
395 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
396 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
398 #define CONFIG_ETHPRIME "eTSEC1"
400 #endif /* CONFIG_TSEC_ENET */
402 #ifdef CONFIG_PHYS_64BIT
403 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
404 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
406 /* Put physical address into the BAT format */
407 #define BAT_PHYS_ADDR(low, high) \
408 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
409 /* Convert high/low pairs to actual 64-bit value */
410 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
412 /* 32-bit systems just ignore the "high" bits */
413 #define BAT_PHYS_ADDR(low, high) (low)
414 #define PAIRED_PHYS_TO_PHYS(low, high) (low)
420 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
421 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
424 * BAT1 LBC (PIXIS/CF)
426 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
427 CONFIG_SYS_PHYS_ADDR_HIGH) \
428 | BATL_PP_RW | BATL_CACHEINHIBIT | \
430 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
432 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
433 CONFIG_SYS_PHYS_ADDR_HIGH) \
434 | BATL_PP_RW | BATL_MEMCOHERENCE)
435 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
438 * BAT2 PCIE1 and PCIE1 MEM
440 * BAT2 Rapidio Memory
443 #define CONFIG_PCI_INDIRECT_BRIDGE
444 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
445 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
446 | BATL_PP_RW | BATL_CACHEINHIBIT \
447 | BATL_GUARDEDSTORAGE)
448 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
450 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
451 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
452 | BATL_PP_RW | BATL_CACHEINHIBIT)
453 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
454 #else /* CONFIG_RIO */
455 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
456 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
457 | BATL_PP_RW | BATL_CACHEINHIBIT | \
459 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
461 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
462 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
463 | BATL_PP_RW | BATL_CACHEINHIBIT)
464 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
470 #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
471 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
472 | BATL_PP_RW | BATL_CACHEINHIBIT \
473 | BATL_GUARDEDSTORAGE)
474 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
476 #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
477 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
478 | BATL_PP_RW | BATL_CACHEINHIBIT)
479 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
481 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
482 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
483 | BATL_PP_RW | BATL_CACHEINHIBIT \
484 | BATL_GUARDEDSTORAGE)
485 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
486 | BATU_BL_1M | BATU_VS | BATU_VP)
487 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
488 | BATL_PP_RW | BATL_CACHEINHIBIT)
489 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
493 * BAT4 PCIE1_IO and PCIE2_IO
495 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
496 CONFIG_SYS_PHYS_ADDR_HIGH) \
497 | BATL_PP_RW | BATL_CACHEINHIBIT \
498 | BATL_GUARDEDSTORAGE)
499 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
501 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
502 CONFIG_SYS_PHYS_ADDR_HIGH) \
503 | BATL_PP_RW | BATL_CACHEINHIBIT)
504 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
507 * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
509 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
510 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
511 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
512 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
517 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
518 CONFIG_SYS_PHYS_ADDR_HIGH) \
519 | BATL_PP_RW | BATL_CACHEINHIBIT \
520 | BATL_GUARDEDSTORAGE)
521 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
523 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
524 CONFIG_SYS_PHYS_ADDR_HIGH) \
525 | BATL_PP_RW | BATL_MEMCOHERENCE)
526 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
528 /* Map the last 1M of flash where we're running from reset */
529 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
530 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
531 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
532 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
534 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
537 * BAT7 FREE - used later for tmp mappings
539 #define CONFIG_SYS_DBAT7L 0x00000000
540 #define CONFIG_SYS_DBAT7U 0x00000000
541 #define CONFIG_SYS_IBAT7L 0x00000000
542 #define CONFIG_SYS_IBAT7U 0x00000000
548 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
549 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
554 #define CONFIG_BOOTP_BOOTFILESIZE
556 #undef CONFIG_WATCHDOG /* watchdog disabled */
559 * Miscellaneous configurable options
561 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
564 * For booting Linux, the board info and command line data
565 * have to be in the first 8 MB of memory, since this is
566 * the maximum mapped by the Linux kernel during initialization.
568 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
569 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */
571 #if defined(CONFIG_CMD_KGDB)
572 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
576 * Environment Configuration
579 #define CONFIG_HAS_ETH0 1
580 #define CONFIG_HAS_ETH1 1
581 #define CONFIG_HAS_ETH2 1
582 #define CONFIG_HAS_ETH3 1
584 #define CONFIG_IPADDR 192.168.1.100
586 #define CONFIG_HOSTNAME "unknown"
587 #define CONFIG_ROOTPATH "/opt/nfsroot"
588 #define CONFIG_BOOTFILE "uImage"
589 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
591 #define CONFIG_SERVERIP 192.168.1.1
592 #define CONFIG_GATEWAYIP 192.168.1.1
593 #define CONFIG_NETMASK 255.255.255.0
595 /* default location for tftp and bootm */
596 #define CONFIG_LOADADDR 0x10000000
598 #define CONFIG_EXTRA_ENV_SETTINGS \
600 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
601 "tftpflash=tftpboot $loadaddr $uboot; " \
602 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
604 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
606 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
608 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
610 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
612 "consoledev=ttyS0\0" \
613 "ramdiskaddr=0x18000000\0" \
614 "ramdiskfile=your.ramdisk.u-boot\0" \
615 "fdtaddr=0x17c00000\0" \
616 "fdtfile=mpc8641_hpcn.dtb\0" \
617 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
618 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
621 #define CONFIG_NFSBOOTCOMMAND \
622 "setenv bootargs root=/dev/nfs rw " \
623 "nfsroot=$serverip:$rootpath " \
624 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
625 "console=$consoledev,$baudrate $othbootargs;" \
626 "tftp $loadaddr $bootfile;" \
627 "tftp $fdtaddr $fdtfile;" \
628 "bootm $loadaddr - $fdtaddr"
630 #define CONFIG_RAMBOOTCOMMAND \
631 "setenv bootargs root=/dev/ram rw " \
632 "console=$consoledev,$baudrate $othbootargs;" \
633 "tftp $ramdiskaddr $ramdiskfile;" \
634 "tftp $loadaddr $bootfile;" \
635 "tftp $fdtaddr $fdtfile;" \
636 "bootm $loadaddr $ramdiskaddr $fdtaddr"
638 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
640 #endif /* __CONFIG_H */