2 * Copyright 2006 Freescale Semiconductor.
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MPC8641HPCN board configuration file
28 * Make sure you change the MAC address and other network params first,
29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
35 /* High Level Configuration Options */
36 #define CONFIG_MPC86xx 1 /* MPC86xx */
37 #define CONFIG_MPC8641 1 /* MPC8641 specific */
38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
39 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
41 /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */
44 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
47 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
50 * virtual address to be used for temporary mappings. There
51 * should be 128k free at this VA.
53 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
56 * set this to enable Rapid IO. PCI and RIO are mutually exclusive
58 /*#define CONFIG_RIO 1*/
60 #ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */
61 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
62 #define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */
63 #define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */
64 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
65 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
67 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
69 #define CONFIG_TSEC_ENET /* tsec ethernet support */
70 #define CONFIG_ENV_OVERWRITE
72 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
74 #define CONFIG_ALTIVEC 1
77 * L2CR setup -- make sure this is right for your board!
81 #define L2_ENABLE (L2CR_L2E)
83 #ifndef CONFIG_SYS_CLK_FREQ
85 extern unsigned long get_board_sys_clk(unsigned long dummy);
87 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
90 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
92 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
93 #define CONFIG_SYS_MEMTEST_END 0x00400000
96 * With the exception of PCI Memory and Rapid IO, most devices will simply
97 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
98 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
100 #ifdef CONFIG_PHYS_64BIT
101 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL
103 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0
107 * Base addresses -- Note these are effective addresses where the
108 * actual resources get mapped (not physical addresses)
110 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
111 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
112 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
114 /* Physical addresses */
115 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
116 #ifdef CONFIG_PHYS_64BIT
117 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
119 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
122 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
123 #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
128 #define CONFIG_FSL_DDR2
129 #undef CONFIG_FSL_DDR_INTERACTIVE
130 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
131 #define CONFIG_DDR_SPD
133 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
134 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
136 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
137 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
138 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
139 #define CONFIG_VERY_BIG_RAM
141 #define MPC86xx_DDR_SDRAM_CLK_CNTL
143 #define CONFIG_NUM_DDR_CONTROLLERS 2
144 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
145 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
148 * I2C addresses of SPD EEPROMs
150 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
151 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
152 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
153 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
157 * These are used when DDR doesn't use SPD.
159 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
160 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
161 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
162 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
163 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
164 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
165 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
166 #define CONFIG_SYS_DDR_MODE_1 0x00480432
167 #define CONFIG_SYS_DDR_MODE_2 0x00000000
168 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
169 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
170 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
171 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
172 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
173 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
174 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
176 #define CONFIG_ID_EEPROM
177 #define CONFIG_SYS_I2C_EEPROM_NXID
178 #define CONFIG_ID_EEPROM
179 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
180 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
182 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
183 #define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \
184 | CONFIG_SYS_PHYS_ADDR_HIGH)
187 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
189 /* Convert an address into the right format for the BR registers */
190 #ifdef CONFIG_PHYS_64BIT
191 #define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
192 ((x & 0x300000000ULL) >> 19)))
194 #define BR_PHYS_ADDR(x) (x & 0xffff8000)
197 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
198 | 0x00001001) /* port size 16bit */
199 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
201 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
202 | 0x00001001) /* port size 16bit */
203 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
205 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
206 | 0x00000801) /* port size 8bit */
207 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
210 * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
211 * The PIXIS and CF by themselves aren't large enough to take up the 128k
212 * required for the smallest BAT mapping, so there's a 64k hole.
214 #define CONFIG_SYS_LBC_BASE 0xffde0000
215 #define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \
216 | CONFIG_SYS_PHYS_ADDR_HIGH)
218 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
219 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
220 #define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000)
221 #define PIXIS_SIZE 0x00008000 /* 32k */
222 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
223 #define PIXIS_VER 0x1 /* Board version at offset 1 */
224 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
225 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
226 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
227 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
228 #define PIXIS_VCTL 0x10 /* VELA Control Register */
229 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
230 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
231 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
232 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
233 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
234 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
235 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
236 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
238 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
239 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
240 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
242 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
243 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
245 #undef CONFIG_SYS_FLASH_CHECKSUM
246 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
247 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
248 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
249 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
251 #define CONFIG_FLASH_CFI_DRIVER
252 #define CONFIG_SYS_FLASH_CFI
253 #define CONFIG_SYS_FLASH_EMPTY_INFO
255 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
256 #define CONFIG_SYS_RAMBOOT
258 #undef CONFIG_SYS_RAMBOOT
261 #if defined(CONFIG_SYS_RAMBOOT)
262 #undef CONFIG_SPD_EEPROM
263 #define CONFIG_SYS_SDRAM_SIZE 256
266 #undef CONFIG_CLOCKS_IN_MHZ
268 #define CONFIG_L1_INIT_RAM
269 #define CONFIG_SYS_INIT_RAM_LOCK 1
270 #ifndef CONFIG_SYS_INIT_RAM_LOCK
271 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
273 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
275 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
277 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
278 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
279 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
281 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
282 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
285 #define CONFIG_CONS_INDEX 1
286 #undef CONFIG_SERIAL_SOFTWARE_FIFO
287 #define CONFIG_SYS_NS16550
288 #define CONFIG_SYS_NS16550_SERIAL
289 #define CONFIG_SYS_NS16550_REG_SIZE 1
290 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
292 #define CONFIG_SYS_BAUDRATE_TABLE \
293 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
295 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
296 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
298 /* Use the HUSH parser */
299 #define CONFIG_SYS_HUSH_PARSER
300 #ifdef CONFIG_SYS_HUSH_PARSER
301 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
305 * Pass open firmware flat tree to kernel
307 #define CONFIG_OF_LIBFDT 1
308 #define CONFIG_OF_BOARD_SETUP 1
309 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
312 #define CONFIG_SYS_64BIT_VSPRINTF 1
313 #define CONFIG_SYS_64BIT_STRTOUL 1
318 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
319 #define CONFIG_HARD_I2C /* I2C with hardware support*/
320 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
321 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
322 #define CONFIG_SYS_I2C_SLAVE 0x7F
323 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
324 #define CONFIG_SYS_I2C_OFFSET 0x3100
329 #define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */
330 #ifdef CONFIG_PHYS_64BIT
331 #define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL
333 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
335 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
339 * Addresses are mapped 1-1.
341 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
342 #ifdef CONFIG_PHYS_64BIT
343 #define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL
345 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
347 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
348 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
349 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
350 #define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \
351 | CONFIG_SYS_PHYS_ADDR_HIGH)
352 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */
355 #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
356 #define _IO_BASE 0x00000000
358 #define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MEM_BASE \
359 + CONFIG_SYS_PCI1_MEM_SIZE)
360 #define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \
361 + CONFIG_SYS_PCI1_MEM_SIZE)
362 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
363 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
364 #define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \
365 + CONFIG_SYS_PCI1_IO_SIZE)
366 #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \
367 + CONFIG_SYS_PCI1_IO_SIZE)
368 #define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE
370 #if defined(CONFIG_PCI)
372 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
374 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
376 #define CONFIG_NET_MULTI
377 #define CONFIG_PCI_PNP /* do pci plug-and-play */
379 #define CONFIG_RTL8139
381 #undef CONFIG_EEPRO100
384 /************************************************************
386 ************************************************************/
387 #define CONFIG_PCI_OHCI 1
388 #define CONFIG_USB_OHCI_NEW 1
389 #define CONFIG_USB_KEYBOARD 1
390 #define CONFIG_SYS_DEVICE_DEREGISTER
391 #define CONFIG_SYS_USB_EVENT_POLL 1
392 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
393 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
394 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
396 /*PCIE video card used*/
397 #define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_VIRT
399 /*PCI video card used*/
400 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
405 #if defined(CONFIG_VIDEO)
406 #define CONFIG_BIOSEMU
407 #define CONFIG_CFB_CONSOLE
408 #define CONFIG_VIDEO_SW_CURSOR
409 #define CONFIG_VGA_AS_SINGLE_DEVICE
410 #define CONFIG_ATI_RADEON_FB
411 #define CONFIG_VIDEO_LOGO
412 /*#define CONFIG_CONSOLE_CURSOR*/
413 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT
416 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
418 #define CONFIG_DOS_PARTITION
419 #define CONFIG_SCSI_AHCI
421 #ifdef CONFIG_SCSI_AHCI
422 #define CONFIG_SATA_ULI5288
423 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
424 #define CONFIG_SYS_SCSI_MAX_LUN 1
425 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
426 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
429 #define CONFIG_MPC86XX_PCI2
431 #endif /* CONFIG_PCI */
433 #if defined(CONFIG_TSEC_ENET)
435 #ifndef CONFIG_NET_MULTI
436 #define CONFIG_NET_MULTI 1
439 #define CONFIG_MII 1 /* MII PHY management */
441 #define CONFIG_TSEC1 1
442 #define CONFIG_TSEC1_NAME "eTSEC1"
443 #define CONFIG_TSEC2 1
444 #define CONFIG_TSEC2_NAME "eTSEC2"
445 #define CONFIG_TSEC3 1
446 #define CONFIG_TSEC3_NAME "eTSEC3"
447 #define CONFIG_TSEC4 1
448 #define CONFIG_TSEC4_NAME "eTSEC4"
450 #define TSEC1_PHY_ADDR 0
451 #define TSEC2_PHY_ADDR 1
452 #define TSEC3_PHY_ADDR 2
453 #define TSEC4_PHY_ADDR 3
454 #define TSEC1_PHYIDX 0
455 #define TSEC2_PHYIDX 0
456 #define TSEC3_PHYIDX 0
457 #define TSEC4_PHYIDX 0
458 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
459 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
460 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
461 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
463 #define CONFIG_ETHPRIME "eTSEC1"
465 #endif /* CONFIG_TSEC_ENET */
467 /* Contort an addr into the format needed for BATs */
468 #ifdef CONFIG_PHYS_64BIT
469 #define BAT_PHYS_ADDR(x) ((unsigned long) \
470 ((x & 0x00000000ffffffffULL) | \
471 ((x & 0x0000000e00000000ULL) >> 24) | \
472 ((x & 0x0000000100000000ULL) >> 30)))
474 #define BAT_PHYS_ADDR(x) (x)
478 /* Put high physical address bits into the BAT format */
479 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
480 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
485 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
486 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
487 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
488 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
491 * BAT1 LBC (PIXIS/CF)
493 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
494 | BATL_PP_RW | BATL_CACHEINHIBIT | \
496 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
498 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
499 | BATL_PP_RW | BATL_MEMCOHERENCE)
500 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
503 * BAT2 PCI1 and PCI1 MEM
505 * BAT2 Rapidio Memory
508 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
509 | BATL_PP_RW | BATL_CACHEINHIBIT \
510 | BATL_GUARDEDSTORAGE)
511 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_1G \
513 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
514 | BATL_PP_RW | BATL_CACHEINHIBIT)
515 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
516 #else /* CONFIG_RIO */
517 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
518 | BATL_PP_RW | BATL_CACHEINHIBIT | \
520 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \
522 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
523 | BATL_PP_RW | BATL_CACHEINHIBIT)
525 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
526 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
527 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
528 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
529 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
534 * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs
535 * instead. The assembler chokes on ULL.
537 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \
538 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
539 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
540 | BATL_PP_RW | BATL_CACHEINHIBIT \
541 | BATL_GUARDEDSTORAGE)
542 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
544 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \
545 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
546 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
547 | BATL_PP_RW | BATL_CACHEINHIBIT)
548 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
550 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
551 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
552 | BATL_PP_RW | BATL_CACHEINHIBIT \
553 | BATL_GUARDEDSTORAGE)
554 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
555 | BATU_BL_1M | BATU_VS | BATU_VP)
556 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
557 | BATL_PP_RW | BATL_CACHEINHIBIT)
558 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
562 * BAT4 PCI1_IO and PCI2_IO
564 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
565 | BATL_PP_RW | BATL_CACHEINHIBIT \
566 | BATL_GUARDEDSTORAGE)
567 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \
569 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
570 | BATL_PP_RW | BATL_CACHEINHIBIT)
571 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
574 * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
576 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
577 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
578 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
579 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
584 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
585 | BATL_PP_RW | BATL_CACHEINHIBIT \
586 | BATL_GUARDEDSTORAGE)
587 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
589 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
590 | BATL_PP_RW | BATL_MEMCOHERENCE)
591 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
593 /* Map the last 1M of flash where we're running from reset */
594 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
595 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
596 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
597 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
599 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
602 * BAT7 FREE - used later for tmp mappings
604 #define CONFIG_SYS_DBAT7L 0x00000000
605 #define CONFIG_SYS_DBAT7U 0x00000000
606 #define CONFIG_SYS_IBAT7L 0x00000000
607 #define CONFIG_SYS_IBAT7U 0x00000000
612 #ifndef CONFIG_SYS_RAMBOOT
613 #define CONFIG_ENV_IS_IN_FLASH 1
614 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
615 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
617 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
618 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
620 #define CONFIG_ENV_SIZE 0x2000
622 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
623 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
629 #define CONFIG_BOOTP_BOOTFILESIZE
630 #define CONFIG_BOOTP_BOOTPATH
631 #define CONFIG_BOOTP_GATEWAY
632 #define CONFIG_BOOTP_HOSTNAME
636 * Command line configuration.
638 #include <config_cmd_default.h>
640 #define CONFIG_CMD_PING
641 #define CONFIG_CMD_I2C
642 #define CONFIG_CMD_REGINFO
644 #if defined(CONFIG_SYS_RAMBOOT)
645 #undef CONFIG_CMD_ENV
648 #if defined(CONFIG_PCI)
649 #define CONFIG_CMD_PCI
650 #define CONFIG_CMD_SCSI
651 #define CONFIG_CMD_EXT2
652 #define CONFIG_CMD_USB
656 #undef CONFIG_WATCHDOG /* watchdog disabled */
659 * Miscellaneous configurable options
661 #define CONFIG_SYS_LONGHELP /* undef to save memory */
662 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
663 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
664 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
666 #if defined(CONFIG_CMD_KGDB)
667 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
669 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
672 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
673 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
674 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
675 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
678 * For booting Linux, the board info and command line data
679 * have to be in the first 8 MB of memory, since this is
680 * the maximum mapped by the Linux kernel during initialization.
682 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
685 * Internal Definitions
689 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
690 #define BOOTFLAG_WARM 0x02 /* Software reboot */
692 #if defined(CONFIG_CMD_KGDB)
693 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
694 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
698 * Environment Configuration
701 /* The mac addresses for all ethernet interface */
702 #if defined(CONFIG_TSEC_ENET)
703 #define CONFIG_ETHADDR 00:E0:0C:00:00:01
704 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
705 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
706 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
709 #define CONFIG_HAS_ETH0 1
710 #define CONFIG_HAS_ETH1 1
711 #define CONFIG_HAS_ETH2 1
712 #define CONFIG_HAS_ETH3 1
714 #define CONFIG_IPADDR 192.168.1.100
716 #define CONFIG_HOSTNAME unknown
717 #define CONFIG_ROOTPATH /opt/nfsroot
718 #define CONFIG_BOOTFILE uImage
719 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
721 #define CONFIG_SERVERIP 192.168.1.1
722 #define CONFIG_GATEWAYIP 192.168.1.1
723 #define CONFIG_NETMASK 255.255.255.0
725 /* default location for tftp and bootm */
726 #define CONFIG_LOADADDR 1000000
728 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
729 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
731 #define CONFIG_BAUDRATE 115200
733 #define CONFIG_EXTRA_ENV_SETTINGS \
735 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
736 "tftpflash=tftpboot $loadaddr $uboot; " \
737 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
738 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
739 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
740 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
741 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
742 "consoledev=ttyS0\0" \
743 "ramdiskaddr=2000000\0" \
744 "ramdiskfile=your.ramdisk.u-boot\0" \
746 "fdtfile=mpc8641_hpcn.dtb\0" \
747 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
748 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
752 #define CONFIG_NFSBOOTCOMMAND \
753 "setenv bootargs root=/dev/nfs rw " \
754 "nfsroot=$serverip:$rootpath " \
755 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
756 "console=$consoledev,$baudrate $othbootargs;" \
757 "tftp $loadaddr $bootfile;" \
758 "tftp $fdtaddr $fdtfile;" \
759 "bootm $loadaddr - $fdtaddr"
761 #define CONFIG_RAMBOOTCOMMAND \
762 "setenv bootargs root=/dev/ram rw " \
763 "console=$consoledev,$baudrate $othbootargs;" \
764 "tftp $ramdiskaddr $ramdiskfile;" \
765 "tftp $loadaddr $bootfile;" \
766 "tftp $fdtaddr $fdtfile;" \
767 "bootm $loadaddr $ramdiskaddr $fdtaddr"
769 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
771 #endif /* __CONFIG_H */