include/configs/MPC8641HPCN.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2006, 2010-2011 Freescale Semiconductor.
   4  *
   5  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   6  */
   7
   8 /*
   9  * MPC8641HPCN board configuration file
  10  *
  11  * Make sure you change the MAC address and other network params first,
  12  * search for CONFIG_SERVERIP, etc. in this file.
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /* High Level Configuration Options */
  19 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  20 #define CONFIG_ADDR_MAP         1       /* Use addr map */
  21
  22 /*
  23  * default CCSRBAR is at 0xff700000
  24  * assume U-Boot is less than 0.5MB
  25  */
  26
  27 #ifdef RUN_DIAG
  28 #define CONFIG_SYS_DIAG_ADDR         CONFIG_SYS_FLASH_BASE
  29 #endif
  30
  31 /*
  32  * virtual address to be used for temporary mappings.  There
  33  * should be 128k free at this VA.
  34  */
  35 #define CONFIG_SYS_SCRATCH_VA   0xe0000000
  36
  37 #define CONFIG_SYS_SRIO
  38 #define CONFIG_SRIO1                    /* SRIO port 1 */
  39
  40 #define CONFIG_PCIE1            1       /* PCIE controller 1 (ULI bridge) */
  41 #define CONFIG_PCIE2            1       /* PCIE controller 2 (slot) */
  42 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  43 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  44
  45 #define CONFIG_ENV_OVERWRITE
  46
  47 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  48 #define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
  49 #define CONFIG_SYS_NUM_ADDR_MAP 8       /* Number of addr map slots = 8 dbats */
  50
  51 #define CONFIG_ALTIVEC          1
  52
  53 /*
  54  * L2CR setup -- make sure this is right for your board!
  55  */
  56 #define CONFIG_SYS_L2
  57 #define L2_INIT         0
  58 #define L2_ENABLE       (L2CR_L2E)
  59
  60 #ifndef CONFIG_SYS_CLK_FREQ
  61 #ifndef __ASSEMBLY__
  62 extern unsigned long get_board_sys_clk(unsigned long dummy);
  63 #endif
  64 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  65 #endif
  66
  67 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  68 #define CONFIG_SYS_MEMTEST_END          0x00400000
  69
  70 /*
  71  * With the exception of PCI Memory and Rapid IO, most devices will simply
  72  * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
  73  * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
  74  */
  75 #ifdef CONFIG_PHYS_64BIT
  76 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
  77 #else
  78 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
  79 #endif
  80
  81 /*
  82  * Base addresses -- Note these are effective addresses where the
  83  * actual resources get mapped (not physical addresses)
  84  */
  85 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
  86 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  87
  88 /* Physical addresses */
  89 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  90 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    CONFIG_SYS_PHYS_ADDR_HIGH
  91 #define CONFIG_SYS_CCSRBAR_PHYS \
  92         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
  93                             CONFIG_SYS_CCSRBAR_PHYS_HIGH)
  94
  95 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
  96
  97 /*
  98  * DDR Setup
  99  */
 100 #define CONFIG_FSL_DDR_INTERACTIVE
 101 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 102 #define CONFIG_DDR_SPD
 103
 104 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 105 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 106
 107 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 108 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 109 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
 110 #define CONFIG_VERY_BIG_RAM
 111
 112 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 113 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 114
 115 /*
 116  * I2C addresses of SPD EEPROMs
 117  */
 118 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 119 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 0 DIMM 1 */
 120 #define SPD_EEPROM_ADDRESS3     0x53    /* CTLR 1 DIMM 0 */
 121 #define SPD_EEPROM_ADDRESS4     0x54    /* CTLR 1 DIMM 1 */
 122
 123 /*
 124  * These are used when DDR doesn't use SPD.
 125  */
 126 #define CONFIG_SYS_SDRAM_SIZE           256             /* DDR is 256MB */
 127 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
 128 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102      /* Enable, no interleaving */
 129 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 130 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 131 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
 132 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 133 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 134 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 135 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
 136 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 137 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 138 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 139 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 140 #define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 141 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
 142
 143 #define CONFIG_ID_EEPROM
 144 #define CONFIG_SYS_I2C_EEPROM_NXID
 145 #define CONFIG_ID_EEPROM
 146 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 147 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 148
 149 #define CONFIG_SYS_FLASH_BASE           0xef800000     /* start of FLASH 8M */
 150 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW  CONFIG_SYS_FLASH_BASE
 151 #define CONFIG_SYS_FLASH_BASE_PHYS \
 152         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 153                             CONFIG_SYS_PHYS_ADDR_HIGH)
 154
 155 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
 156
 157 #define CONFIG_SYS_BR0_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 158                                  | 0x00001001)  /* port size 16bit */
 159 #define CONFIG_SYS_OR0_PRELIM   0xff806ff7      /* 8MB Boot Flash area*/
 160
 161 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(CF_BASE_PHYS)             \
 162                                  | 0x00001001)  /* port size 16bit */
 163 #define CONFIG_SYS_OR2_PRELIM   0xffffeff7      /* 32k Compact Flash */
 164
 165 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS)  \
 166                                  | 0x00000801) /* port size 8bit */
 167 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32k PIXIS area*/
 168
 169 /*
 170  * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
 171  * The PIXIS and CF by themselves aren't large enough to take up the 128k
 172  * required for the smallest BAT mapping, so there's a 64k hole.
 173  */
 174 #define CONFIG_SYS_LBC_BASE             0xffde0000
 175 #define CONFIG_SYS_LBC_BASE_PHYS_LOW    CONFIG_SYS_LBC_BASE
 176
 177 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 178 #define PIXIS_BASE              (CONFIG_SYS_LBC_BASE + 0x00010000)
 179 #define PIXIS_BASE_PHYS_LOW     (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
 180 #define PIXIS_BASE_PHYS         PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
 181                                                     CONFIG_SYS_PHYS_ADDR_HIGH)
 182 #define PIXIS_SIZE              0x00008000      /* 32k */
 183 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 184 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 185 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 186 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 187 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch register */
 188 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 189 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 190 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 191 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 192 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 193 #define PIXIS_VBOOT_FMAP        0x80    /* VBOOT - CFG_FLASHMAP */
 194 #define PIXIS_VBOOT_FBANK       0x40    /* VBOOT - CFG_FLASHBANK */
 195 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 196 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 197 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 198 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 199 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x40    /* Reset altbank mask*/
 200
 201 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
 202 #define CF_BASE                 (PIXIS_BASE + PIXIS_SIZE)
 203 #define CF_BASE_PHYS            (PIXIS_BASE_PHYS + PIXIS_SIZE)
 204
 205 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 206 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 207
 208 #undef  CONFIG_SYS_FLASH_CHECKSUM
 209 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 210 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 211 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 212 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 213
 214 #define CONFIG_SYS_FLASH_EMPTY_INFO
 215
 216 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 217 #define CONFIG_SYS_RAMBOOT
 218 #else
 219 #undef  CONFIG_SYS_RAMBOOT
 220 #endif
 221
 222 #if defined(CONFIG_SYS_RAMBOOT)
 223 #undef CONFIG_SPD_EEPROM
 224 #define CONFIG_SYS_SDRAM_SIZE   256
 225 #endif
 226
 227 #undef CONFIG_CLOCKS_IN_MHZ
 228
 229 #define CONFIG_SYS_INIT_RAM_LOCK        1
 230 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 231 #define CONFIG_SYS_INIT_RAM_ADDR        0x0fd00000      /* Initial RAM address */
 232 #else
 233 #define CONFIG_SYS_INIT_RAM_ADDR        0xf8400000      /* Initial RAM address */
 234 #endif
 235 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 236
 237 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 238 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 239
 240 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Mon */
 241 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)    /* Reserved for malloc */
 242
 243 /* Serial Port */
 244 #define CONFIG_SYS_NS16550_SERIAL
 245 #define CONFIG_SYS_NS16550_REG_SIZE     1
 246 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 247
 248 #define CONFIG_SYS_BAUDRATE_TABLE  \
 249         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 250
 251 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 252 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 253
 254 /*
 255  * I2C
 256  */
 257 #define CONFIG_SYS_I2C
 258 #define CONFIG_SYS_I2C_FSL
 259 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 260 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 261 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3100
 262 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 263
 264 /*
 265  * RapidIO MMU
 266  */
 267 #define CONFIG_SYS_SRIO1_MEM_BASE       0x80000000      /* base address */
 268 #ifdef CONFIG_PHYS_64BIT
 269 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW   0x00000000
 270 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x0000000c
 271 #else
 272 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW   CONFIG_SYS_SRIO1_MEM_BASE
 273 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x00000000
 274 #endif
 275 #define CONFIG_SYS_SRIO1_MEM_PHYS \
 276         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 277                             CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
 278 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 128M */
 279
 280 /*
 281  * General PCI
 282  * Addresses are mapped 1-1.
 283  */
 284
 285 #define CONFIG_SYS_PCIE1_NAME           "ULI"
 286 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 287 #ifdef CONFIG_PHYS_64BIT
 288 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 289 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW   0x00000000
 290 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH  0x0000000c
 291 #else
 292 #define CONFIG_SYS_PCIE1_MEM_BUS        CONFIG_SYS_PCIE1_MEM_VIRT
 293 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW   CONFIG_SYS_PCIE1_MEM_VIRT
 294 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH  0x00000000
 295 #endif
 296 #define CONFIG_SYS_PCIE1_MEM_PHYS \
 297         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 298                             CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
 299 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 300 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 301 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 302 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW    CONFIG_SYS_PCIE1_IO_VIRT
 303 #define CONFIG_SYS_PCIE1_IO_PHYS \
 304         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 305                             CONFIG_SYS_PHYS_ADDR_HIGH)
 306 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64K */
 307
 308 #ifdef CONFIG_PHYS_64BIT
 309 /*
 310  * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
 311  * This will increase the amount of PCI address space available for
 312  * for mapping RAM.
 313  */
 314 #define CONFIG_SYS_PCIE2_MEM_BUS        CONFIG_SYS_PCIE1_MEM_BUS
 315 #else
 316 #define CONFIG_SYS_PCIE2_MEM_BUS        (CONFIG_SYS_PCIE1_MEM_BUS \
 317                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 318 #endif
 319 #define CONFIG_SYS_PCIE2_MEM_VIRT       (CONFIG_SYS_PCIE1_MEM_VIRT \
 320                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 321 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW   (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
 322                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 323 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH  CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
 324 #define CONFIG_SYS_PCIE2_MEM_PHYS       (CONFIG_SYS_PCIE1_MEM_PHYS \
 325                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 326 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 327 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 328 #define CONFIG_SYS_PCIE2_IO_VIRT        (CONFIG_SYS_PCIE1_IO_VIRT \
 329                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 330 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW    (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
 331                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 332 #define CONFIG_SYS_PCIE2_IO_PHYS        (CONFIG_SYS_PCIE1_IO_PHYS \
 333                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 334 #define CONFIG_SYS_PCIE2_IO_SIZE        CONFIG_SYS_PCIE1_IO_SIZE
 335
 336 #if defined(CONFIG_PCI)
 337
 338 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 339
 340 #undef CONFIG_EEPRO100
 341 #undef CONFIG_TULIP
 342
 343 /************************************************************
 344  * USB support
 345  ************************************************************/
 346 #define CONFIG_PCI_OHCI                 1
 347 #define CONFIG_USB_OHCI_NEW             1
 348 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
 349 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 350 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 351
 352 /*PCIE video card used*/
 353 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE2_IO_VIRT
 354
 355 /*PCI video card used*/
 356 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCIE1_IO_VIRT*/
 357
 358 /* video */
 359
 360 #if defined(CONFIG_VIDEO)
 361 #define CONFIG_BIOSEMU
 362 #define CONFIG_ATI_RADEON_FB
 363 #define CONFIG_VIDEO_LOGO
 364 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
 365 #endif
 366
 367 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 368
 369 #ifdef CONFIG_SCSI_AHCI
 370 #define CONFIG_SATA_ULI5288
 371 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 372 #define CONFIG_SYS_SCSI_MAX_LUN 1
 373 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 374 #endif
 375
 376 #endif  /* CONFIG_PCI */
 377
 378 #if defined(CONFIG_TSEC_ENET)
 379 #define CONFIG_TSEC1            1
 380 #define CONFIG_TSEC1_NAME       "eTSEC1"
 381 #define CONFIG_TSEC2            1
 382 #define CONFIG_TSEC2_NAME       "eTSEC2"
 383 #define CONFIG_TSEC3            1
 384 #define CONFIG_TSEC3_NAME       "eTSEC3"
 385 #define CONFIG_TSEC4            1
 386 #define CONFIG_TSEC4_NAME       "eTSEC4"
 387
 388 #define TSEC1_PHY_ADDR          0
 389 #define TSEC2_PHY_ADDR          1
 390 #define TSEC3_PHY_ADDR          2
 391 #define TSEC4_PHY_ADDR          3
 392 #define TSEC1_PHYIDX            0
 393 #define TSEC2_PHYIDX            0
 394 #define TSEC3_PHYIDX            0
 395 #define TSEC4_PHYIDX            0
 396 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 397 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 398 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 399 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 400
 401 #define CONFIG_ETHPRIME         "eTSEC1"
 402
 403 #endif  /* CONFIG_TSEC_ENET */
 404
 405 #ifdef CONFIG_PHYS_64BIT
 406 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
 407 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
 408
 409 /* Put physical address into the BAT format */
 410 #define BAT_PHYS_ADDR(low, high) \
 411         (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
 412 /* Convert high/low pairs to actual 64-bit value */
 413 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
 414 #else
 415 /* 32-bit systems just ignore the "high" bits */
 416 #define BAT_PHYS_ADDR(low, high)        (low)
 417 #define PAIRED_PHYS_TO_PHYS(low, high)  (low)
 418 #endif
 419
 420 /*
 421  * BAT0         DDR
 422  */
 423 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 424 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 425
 426 /*
 427  * BAT1         LBC (PIXIS/CF)
 428  */
 429 #define CONFIG_SYS_DBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
 430                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 431                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 432                                  BATL_GUARDEDSTORAGE)
 433 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
 434                                  | BATU_VS | BATU_VP)
 435 #define CONFIG_SYS_IBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
 436                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 437                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 438 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 439
 440 /* if CONFIG_PCI:
 441  * BAT2         PCIE1 and PCIE1 MEM
 442  * if CONFIG_RIO
 443  * BAT2         Rapidio Memory
 444  */
 445 #ifdef CONFIG_PCI
 446 #define CONFIG_PCI_INDIRECT_BRIDGE
 447 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 448                                                CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
 449                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 450                                  | BATL_GUARDEDSTORAGE)
 451 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
 452                                  | BATU_VS | BATU_VP)
 453 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 454                                                CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
 455                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 456 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 457 #else /* CONFIG_RIO */
 458 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 459                                                CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
 460                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 461                                  BATL_GUARDEDSTORAGE)
 462 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
 463                                  | BATU_VS | BATU_VP)
 464 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 465                                                CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
 466                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 467 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 468 #endif
 469
 470 /*
 471  * BAT3         CCSR Space
 472  */
 473 #define CONFIG_SYS_DBAT3L       (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
 474                                                CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 475                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 476                                  | BATL_GUARDEDSTORAGE)
 477 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
 478                                  | BATU_VP)
 479 #define CONFIG_SYS_IBAT3L       (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
 480                                                CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 481                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 482 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 483
 484 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 485 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 486                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 487                                        | BATL_GUARDEDSTORAGE)
 488 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 489                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 490 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 491                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 492 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 493 #endif
 494
 495 /*
 496  * BAT4         PCIE1_IO and PCIE2_IO
 497  */
 498 #define CONFIG_SYS_DBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 499                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 500                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 501                                  | BATL_GUARDEDSTORAGE)
 502 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
 503                                  | BATU_VS | BATU_VP)
 504 #define CONFIG_SYS_IBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 505                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 506                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 507 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 508
 509 /*
 510  * BAT5         Init RAM for stack in the CPU DCache (no backing memory)
 511  */
 512 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 513 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 514 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 515 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 516
 517 /*
 518  * BAT6         FLASH
 519  */
 520 #define CONFIG_SYS_DBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 521                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 522                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 523                                  | BATL_GUARDEDSTORAGE)
 524 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
 525                                  | BATU_VP)
 526 #define CONFIG_SYS_IBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 527                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 528                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 529 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 530
 531 /* Map the last 1M of flash where we're running from reset */
 532 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 533                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 534 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 535 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 536                                  | BATL_MEMCOHERENCE)
 537 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 538
 539 /*
 540  * BAT7         FREE - used later for tmp mappings
 541  */
 542 #define CONFIG_SYS_DBAT7L 0x00000000
 543 #define CONFIG_SYS_DBAT7U 0x00000000
 544 #define CONFIG_SYS_IBAT7L 0x00000000
 545 #define CONFIG_SYS_IBAT7U 0x00000000
 546
 547 /*
 548  * Environment
 549  */
 550 #ifndef CONFIG_SYS_RAMBOOT
 551     #define CONFIG_ENV_ADDR             \
 552                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 553     #define CONFIG_ENV_SECT_SIZE                0x10000 /* 64K(one sector) for env */
 554 #else
 555     #define CONFIG_ENV_ADDR             (CONFIG_SYS_MONITOR_BASE - 0x1000)
 556 #endif
 557 #define CONFIG_ENV_SIZE         0x2000
 558
 559 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 560 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 561
 562 /*
 563  * BOOTP options
 564  */
 565 #define CONFIG_BOOTP_BOOTFILESIZE
 566
 567 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 568
 569 /*
 570  * Miscellaneous configurable options
 571  */
 572 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 573
 574 /*
 575  * For booting Linux, the board info and command line data
 576  * have to be in the first 8 MB of memory, since this is
 577  * the maximum mapped by the Linux kernel during initialization.
 578  */
 579 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 580 #define CONFIG_SYS_BOOTM_LEN    (256 << 20)     /* Increase max gunzip size */
 581
 582 #if defined(CONFIG_CMD_KGDB)
 583     #define CONFIG_KGDB_BAUDRATE        230400  /* speed to run kgdb serial port */
 584 #endif
 585
 586 /*
 587  * Environment Configuration
 588  */
 589
 590 #define CONFIG_HAS_ETH0         1
 591 #define CONFIG_HAS_ETH1         1
 592 #define CONFIG_HAS_ETH2         1
 593 #define CONFIG_HAS_ETH3         1
 594
 595 #define CONFIG_IPADDR           192.168.1.100
 596
 597 #define CONFIG_HOSTNAME         "unknown"
 598 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 599 #define CONFIG_BOOTFILE         "uImage"
 600 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 601
 602 #define CONFIG_SERVERIP         192.168.1.1
 603 #define CONFIG_GATEWAYIP        192.168.1.1
 604 #define CONFIG_NETMASK          255.255.255.0
 605
 606 /* default location for tftp and bootm */
 607 #define CONFIG_LOADADDR         0x10000000
 608
 609 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 610         "netdev=eth0\0"                                                 \
 611         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 612         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 613                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 614                         " +$filesize; " \
 615                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 616                         " +$filesize; " \
 617                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 618                         " $filesize; "  \
 619                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 620                         " +$filesize; " \
 621                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 622                         " $filesize\0"  \
 623         "consoledev=ttyS0\0"                                            \
 624         "ramdiskaddr=0x18000000\0"                                              \
 625         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 626         "fdtaddr=0x17c00000\0"                                          \
 627         "fdtfile=mpc8641_hpcn.dtb\0"                                    \
 628         "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"                        \
 629         "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
 630         "maxcpus=2"
 631
 632 #define CONFIG_NFSBOOTCOMMAND                                           \
 633         "setenv bootargs root=/dev/nfs rw "                             \
 634               "nfsroot=$serverip:$rootpath "                            \
 635               "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 636               "console=$consoledev,$baudrate $othbootargs;"             \
 637         "tftp $loadaddr $bootfile;"                                     \
 638         "tftp $fdtaddr $fdtfile;"                                       \
 639         "bootm $loadaddr - $fdtaddr"
 640
 641 #define CONFIG_RAMBOOTCOMMAND                                           \
 642         "setenv bootargs root=/dev/ram rw "                             \
 643               "console=$consoledev,$baudrate $othbootargs;"             \
 644         "tftp $ramdiskaddr $ramdiskfile;"                               \
 645         "tftp $loadaddr $bootfile;"                                     \
 646         "tftp $fdtaddr $fdtfile;"                                       \
 647         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 648
 649 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 650
 651 #endif  /* __CONFIG_H */