include/configs/MPC8641HPCN.h

   1 /*
   2  * Copyright 2006, 2010-2011 Freescale Semiconductor.
   3  *
   4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * MPC8641HPCN board configuration file
  11  *
  12  * Make sure you change the MAC address and other network params first,
  13  * search for CONFIG_SERVERIP, etc. in this file.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /* High Level Configuration Options */
  20 #define CONFIG_MPC8641          1       /* MPC8641 specific */
  21 #define CONFIG_MPC8641HPCN      1       /* MPC8641HPCN board specific */
  22 #define CONFIG_MP               1       /* support multiple processors */
  23 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  24 #define CONFIG_ADDR_MAP         1       /* Use addr map */
  25
  26 /*
  27  * default CCSRBAR is at 0xff700000
  28  * assume U-Boot is less than 0.5MB
  29  */
  30 #define CONFIG_SYS_TEXT_BASE    0xeff00000
  31
  32 #ifdef RUN_DIAG
  33 #define CONFIG_SYS_DIAG_ADDR         CONFIG_SYS_FLASH_BASE
  34 #endif
  35
  36 /*
  37  * virtual address to be used for temporary mappings.  There
  38  * should be 128k free at this VA.
  39  */
  40 #define CONFIG_SYS_SCRATCH_VA   0xe0000000
  41
  42 #define CONFIG_SYS_SRIO
  43 #define CONFIG_SRIO1                    /* SRIO port 1 */
  44
  45 #define CONFIG_PCIE1            1       /* PCIE controller 1 (ULI bridge) */
  46 #define CONFIG_PCIE2            1       /* PCIE controller 2 (slot) */
  47 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  48 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  49 #define CONFIG_FSL_LAW          1       /* Use common FSL law init code */
  50
  51 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  52 #define CONFIG_ENV_OVERWRITE
  53
  54 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  55 #define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
  56 #define CONFIG_SYS_NUM_ADDR_MAP 8       /* Number of addr map slots = 8 dbats */
  57
  58 #define CONFIG_ALTIVEC          1
  59
  60 /*
  61  * L2CR setup -- make sure this is right for your board!
  62  */
  63 #define CONFIG_SYS_L2
  64 #define L2_INIT         0
  65 #define L2_ENABLE       (L2CR_L2E)
  66
  67 #ifndef CONFIG_SYS_CLK_FREQ
  68 #ifndef __ASSEMBLY__
  69 extern unsigned long get_board_sys_clk(unsigned long dummy);
  70 #endif
  71 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  72 #endif
  73
  74 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  75 #define CONFIG_SYS_MEMTEST_END          0x00400000
  76
  77 /*
  78  * With the exception of PCI Memory and Rapid IO, most devices will simply
  79  * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
  80  * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
  81  */
  82 #ifdef CONFIG_PHYS_64BIT
  83 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
  84 #else
  85 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
  86 #endif
  87
  88 /*
  89  * Base addresses -- Note these are effective addresses where the
  90  * actual resources get mapped (not physical addresses)
  91  */
  92 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  93 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
  94 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  95
  96 /* Physical addresses */
  97 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  98 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    CONFIG_SYS_PHYS_ADDR_HIGH
  99 #define CONFIG_SYS_CCSRBAR_PHYS \
 100         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
 101                             CONFIG_SYS_CCSRBAR_PHYS_HIGH)
 102
 103 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
 104
 105 /*
 106  * DDR Setup
 107  */
 108 #define CONFIG_SYS_FSL_DDR2
 109 #undef CONFIG_FSL_DDR_INTERACTIVE
 110 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 111 #define CONFIG_DDR_SPD
 112
 113 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 114 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 115
 116 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 117 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 118 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
 119 #define CONFIG_VERY_BIG_RAM
 120
 121 #define CONFIG_NUM_DDR_CONTROLLERS      2
 122 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 123 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 124
 125 /*
 126  * I2C addresses of SPD EEPROMs
 127  */
 128 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 129 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 0 DIMM 1 */
 130 #define SPD_EEPROM_ADDRESS3     0x53    /* CTLR 1 DIMM 0 */
 131 #define SPD_EEPROM_ADDRESS4     0x54    /* CTLR 1 DIMM 1 */
 132
 133 /*
 134  * These are used when DDR doesn't use SPD.
 135  */
 136 #define CONFIG_SYS_SDRAM_SIZE           256             /* DDR is 256MB */
 137 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
 138 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102      /* Enable, no interleaving */
 139 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 140 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 141 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
 142 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 143 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 144 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 145 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
 146 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 147 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 148 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 149 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 150 #define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 151 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
 152
 153 #define CONFIG_ID_EEPROM
 154 #define CONFIG_SYS_I2C_EEPROM_NXID
 155 #define CONFIG_ID_EEPROM
 156 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 157 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 158
 159 #define CONFIG_SYS_FLASH_BASE           0xef800000     /* start of FLASH 8M */
 160 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW  CONFIG_SYS_FLASH_BASE
 161 #define CONFIG_SYS_FLASH_BASE_PHYS \
 162         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 163                             CONFIG_SYS_PHYS_ADDR_HIGH)
 164
 165 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
 166
 167 #define CONFIG_SYS_BR0_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 168                                  | 0x00001001)  /* port size 16bit */
 169 #define CONFIG_SYS_OR0_PRELIM   0xff806ff7      /* 8MB Boot Flash area*/
 170
 171 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(CF_BASE_PHYS)             \
 172                                  | 0x00001001)  /* port size 16bit */
 173 #define CONFIG_SYS_OR2_PRELIM   0xffffeff7      /* 32k Compact Flash */
 174
 175 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS)  \
 176                                  | 0x00000801) /* port size 8bit */
 177 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32k PIXIS area*/
 178
 179 /*
 180  * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
 181  * The PIXIS and CF by themselves aren't large enough to take up the 128k
 182  * required for the smallest BAT mapping, so there's a 64k hole.
 183  */
 184 #define CONFIG_SYS_LBC_BASE             0xffde0000
 185 #define CONFIG_SYS_LBC_BASE_PHYS_LOW    CONFIG_SYS_LBC_BASE
 186
 187 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 188 #define PIXIS_BASE              (CONFIG_SYS_LBC_BASE + 0x00010000)
 189 #define PIXIS_BASE_PHYS_LOW     (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
 190 #define PIXIS_BASE_PHYS         PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
 191                                                     CONFIG_SYS_PHYS_ADDR_HIGH)
 192 #define PIXIS_SIZE              0x00008000      /* 32k */
 193 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 194 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 195 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 196 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 197 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch register */
 198 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 199 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 200 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 201 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 202 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 203 #define PIXIS_VBOOT_FMAP        0x80    /* VBOOT - CFG_FLASHMAP */
 204 #define PIXIS_VBOOT_FBANK       0x40    /* VBOOT - CFG_FLASHBANK */
 205 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 206 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 207 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 208 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 209 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x40    /* Reset altbank mask*/
 210
 211 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
 212 #define CF_BASE                 (PIXIS_BASE + PIXIS_SIZE)
 213 #define CF_BASE_PHYS            (PIXIS_BASE_PHYS + PIXIS_SIZE)
 214
 215 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 216 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 217
 218 #undef  CONFIG_SYS_FLASH_CHECKSUM
 219 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 220 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 221 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 222 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 223
 224 #define CONFIG_FLASH_CFI_DRIVER
 225 #define CONFIG_SYS_FLASH_CFI
 226 #define CONFIG_SYS_FLASH_EMPTY_INFO
 227
 228 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 229 #define CONFIG_SYS_RAMBOOT
 230 #else
 231 #undef  CONFIG_SYS_RAMBOOT
 232 #endif
 233
 234 #if defined(CONFIG_SYS_RAMBOOT)
 235 #undef CONFIG_SPD_EEPROM
 236 #define CONFIG_SYS_SDRAM_SIZE   256
 237 #endif
 238
 239 #undef CONFIG_CLOCKS_IN_MHZ
 240
 241 #define CONFIG_SYS_INIT_RAM_LOCK        1
 242 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 243 #define CONFIG_SYS_INIT_RAM_ADDR        0x0fd00000      /* Initial RAM address */
 244 #else
 245 #define CONFIG_SYS_INIT_RAM_ADDR        0xf8400000      /* Initial RAM address */
 246 #endif
 247 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 248
 249 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 250 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 251
 252 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Mon */
 253 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)    /* Reserved for malloc */
 254
 255 /* Serial Port */
 256 #define CONFIG_CONS_INDEX     1
 257 #define CONFIG_SYS_NS16550_SERIAL
 258 #define CONFIG_SYS_NS16550_REG_SIZE     1
 259 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 260
 261 #define CONFIG_SYS_BAUDRATE_TABLE  \
 262         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 263
 264 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 265 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 266
 267 /*
 268  * I2C
 269  */
 270 #define CONFIG_SYS_I2C
 271 #define CONFIG_SYS_I2C_FSL
 272 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 273 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 274 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3100
 275 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 276
 277 /*
 278  * RapidIO MMU
 279  */
 280 #define CONFIG_SYS_SRIO1_MEM_BASE       0x80000000      /* base address */
 281 #ifdef CONFIG_PHYS_64BIT
 282 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW   0x00000000
 283 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x0000000c
 284 #else
 285 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW   CONFIG_SYS_SRIO1_MEM_BASE
 286 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x00000000
 287 #endif
 288 #define CONFIG_SYS_SRIO1_MEM_PHYS \
 289         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 290                             CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
 291 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 128M */
 292
 293 /*
 294  * General PCI
 295  * Addresses are mapped 1-1.
 296  */
 297
 298 #define CONFIG_SYS_PCIE1_NAME           "ULI"
 299 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 300 #ifdef CONFIG_PHYS_64BIT
 301 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 302 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW   0x00000000
 303 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH  0x0000000c
 304 #else
 305 #define CONFIG_SYS_PCIE1_MEM_BUS        CONFIG_SYS_PCIE1_MEM_VIRT
 306 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW   CONFIG_SYS_PCIE1_MEM_VIRT
 307 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH  0x00000000
 308 #endif
 309 #define CONFIG_SYS_PCIE1_MEM_PHYS \
 310         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 311                             CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
 312 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 313 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 314 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 315 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW    CONFIG_SYS_PCIE1_IO_VIRT
 316 #define CONFIG_SYS_PCIE1_IO_PHYS \
 317         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 318                             CONFIG_SYS_PHYS_ADDR_HIGH)
 319 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64K */
 320
 321 #ifdef CONFIG_PHYS_64BIT
 322 /*
 323  * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
 324  * This will increase the amount of PCI address space available for
 325  * for mapping RAM.
 326  */
 327 #define CONFIG_SYS_PCIE2_MEM_BUS        CONFIG_SYS_PCIE1_MEM_BUS
 328 #else
 329 #define CONFIG_SYS_PCIE2_MEM_BUS        (CONFIG_SYS_PCIE1_MEM_BUS \
 330                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 331 #endif
 332 #define CONFIG_SYS_PCIE2_MEM_VIRT       (CONFIG_SYS_PCIE1_MEM_VIRT \
 333                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 334 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW   (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
 335                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 336 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH  CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
 337 #define CONFIG_SYS_PCIE2_MEM_PHYS       (CONFIG_SYS_PCIE1_MEM_PHYS \
 338                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 339 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 340 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 341 #define CONFIG_SYS_PCIE2_IO_VIRT        (CONFIG_SYS_PCIE1_IO_VIRT \
 342                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 343 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW    (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
 344                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 345 #define CONFIG_SYS_PCIE2_IO_PHYS        (CONFIG_SYS_PCIE1_IO_PHYS \
 346                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 347 #define CONFIG_SYS_PCIE2_IO_SIZE        CONFIG_SYS_PCIE1_IO_SIZE
 348
 349 #if defined(CONFIG_PCI)
 350
 351 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 352
 353 #undef CONFIG_EEPRO100
 354 #undef CONFIG_TULIP
 355
 356 /************************************************************
 357  * USB support
 358  ************************************************************/
 359 #define CONFIG_PCI_OHCI                 1
 360 #define CONFIG_USB_OHCI_NEW             1
 361 #define CONFIG_SYS_USB_EVENT_POLL               1
 362 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
 363 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 364 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 365
 366 /*PCIE video card used*/
 367 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE2_IO_VIRT
 368
 369 /*PCI video card used*/
 370 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCIE1_IO_VIRT*/
 371
 372 /* video */
 373
 374 #if defined(CONFIG_VIDEO)
 375 #define CONFIG_BIOSEMU
 376 #define CONFIG_ATI_RADEON_FB
 377 #define CONFIG_VIDEO_LOGO
 378 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
 379 #endif
 380
 381 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 382
 383 #define CONFIG_DOS_PARTITION
 384 #define CONFIG_SCSI_AHCI
 385
 386 #ifdef CONFIG_SCSI_AHCI
 387 #define CONFIG_LIBATA
 388 #define CONFIG_SATA_ULI5288
 389 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 390 #define CONFIG_SYS_SCSI_MAX_LUN 1
 391 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 392 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 393 #endif
 394
 395 #endif  /* CONFIG_PCI */
 396
 397 #if defined(CONFIG_TSEC_ENET)
 398
 399 #define CONFIG_MII              1       /* MII PHY management */
 400
 401 #define CONFIG_TSEC1            1
 402 #define CONFIG_TSEC1_NAME       "eTSEC1"
 403 #define CONFIG_TSEC2            1
 404 #define CONFIG_TSEC2_NAME       "eTSEC2"
 405 #define CONFIG_TSEC3            1
 406 #define CONFIG_TSEC3_NAME       "eTSEC3"
 407 #define CONFIG_TSEC4            1
 408 #define CONFIG_TSEC4_NAME       "eTSEC4"
 409
 410 #define TSEC1_PHY_ADDR          0
 411 #define TSEC2_PHY_ADDR          1
 412 #define TSEC3_PHY_ADDR          2
 413 #define TSEC4_PHY_ADDR          3
 414 #define TSEC1_PHYIDX            0
 415 #define TSEC2_PHYIDX            0
 416 #define TSEC3_PHYIDX            0
 417 #define TSEC4_PHYIDX            0
 418 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 419 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 420 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 421 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 422
 423 #define CONFIG_ETHPRIME         "eTSEC1"
 424
 425 #endif  /* CONFIG_TSEC_ENET */
 426
 427 #ifdef CONFIG_PHYS_64BIT
 428 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
 429 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
 430
 431 /* Put physical address into the BAT format */
 432 #define BAT_PHYS_ADDR(low, high) \
 433         (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
 434 /* Convert high/low pairs to actual 64-bit value */
 435 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
 436 #else
 437 /* 32-bit systems just ignore the "high" bits */
 438 #define BAT_PHYS_ADDR(low, high)        (low)
 439 #define PAIRED_PHYS_TO_PHYS(low, high)  (low)
 440 #endif
 441
 442 /*
 443  * BAT0         DDR
 444  */
 445 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 446 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 447
 448 /*
 449  * BAT1         LBC (PIXIS/CF)
 450  */
 451 #define CONFIG_SYS_DBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
 452                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 453                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 454                                  BATL_GUARDEDSTORAGE)
 455 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
 456                                  | BATU_VS | BATU_VP)
 457 #define CONFIG_SYS_IBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
 458                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 459                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 460 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 461
 462 /* if CONFIG_PCI:
 463  * BAT2         PCIE1 and PCIE1 MEM
 464  * if CONFIG_RIO
 465  * BAT2         Rapidio Memory
 466  */
 467 #ifdef CONFIG_PCI
 468 #define CONFIG_PCI_INDIRECT_BRIDGE
 469 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 470                                                CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
 471                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 472                                  | BATL_GUARDEDSTORAGE)
 473 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
 474                                  | BATU_VS | BATU_VP)
 475 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 476                                                CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
 477                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 478 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 479 #else /* CONFIG_RIO */
 480 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 481                                                CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
 482                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 483                                  BATL_GUARDEDSTORAGE)
 484 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
 485                                  | BATU_VS | BATU_VP)
 486 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 487                                                CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
 488                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 489 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 490 #endif
 491
 492 /*
 493  * BAT3         CCSR Space
 494  */
 495 #define CONFIG_SYS_DBAT3L       (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
 496                                                CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 497                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 498                                  | BATL_GUARDEDSTORAGE)
 499 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
 500                                  | BATU_VP)
 501 #define CONFIG_SYS_IBAT3L       (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
 502                                                CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 503                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 504 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 505
 506 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 507 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 508                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 509                                        | BATL_GUARDEDSTORAGE)
 510 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 511                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 512 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 513                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 514 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 515 #endif
 516
 517 /*
 518  * BAT4         PCIE1_IO and PCIE2_IO
 519  */
 520 #define CONFIG_SYS_DBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 521                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 522                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 523                                  | BATL_GUARDEDSTORAGE)
 524 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
 525                                  | BATU_VS | BATU_VP)
 526 #define CONFIG_SYS_IBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 527                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 528                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 529 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 530
 531 /*
 532  * BAT5         Init RAM for stack in the CPU DCache (no backing memory)
 533  */
 534 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 535 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 536 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 537 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 538
 539 /*
 540  * BAT6         FLASH
 541  */
 542 #define CONFIG_SYS_DBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 543                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 544                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 545                                  | BATL_GUARDEDSTORAGE)
 546 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
 547                                  | BATU_VP)
 548 #define CONFIG_SYS_IBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 549                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 550                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 551 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 552
 553 /* Map the last 1M of flash where we're running from reset */
 554 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 555                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 556 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 557 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 558                                  | BATL_MEMCOHERENCE)
 559 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 560
 561 /*
 562  * BAT7         FREE - used later for tmp mappings
 563  */
 564 #define CONFIG_SYS_DBAT7L 0x00000000
 565 #define CONFIG_SYS_DBAT7U 0x00000000
 566 #define CONFIG_SYS_IBAT7L 0x00000000
 567 #define CONFIG_SYS_IBAT7U 0x00000000
 568
 569 /*
 570  * Environment
 571  */
 572 #ifndef CONFIG_SYS_RAMBOOT
 573     #define CONFIG_ENV_IS_IN_FLASH      1
 574     #define CONFIG_ENV_ADDR             \
 575                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 576     #define CONFIG_ENV_SECT_SIZE                0x10000 /* 64K(one sector) for env */
 577 #else
 578     #define CONFIG_ENV_IS_NOWHERE       1       /* Store ENV in memory only */
 579     #define CONFIG_ENV_ADDR             (CONFIG_SYS_MONITOR_BASE - 0x1000)
 580 #endif
 581 #define CONFIG_ENV_SIZE         0x2000
 582
 583 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 584 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 585
 586 /*
 587  * BOOTP options
 588  */
 589 #define CONFIG_BOOTP_BOOTFILESIZE
 590 #define CONFIG_BOOTP_BOOTPATH
 591 #define CONFIG_BOOTP_GATEWAY
 592 #define CONFIG_BOOTP_HOSTNAME
 593
 594 /*
 595  * Command line configuration.
 596  */
 597 #define CONFIG_CMD_REGINFO
 598
 599 #if defined(CONFIG_PCI)
 600     #define CONFIG_CMD_PCI
 601     #define CONFIG_SCSI
 602 #endif
 603
 604 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 605
 606 /*
 607  * Miscellaneous configurable options
 608  */
 609 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 610 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 611 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 612
 613 #if defined(CONFIG_CMD_KGDB)
 614     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 615 #else
 616     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 617 #endif
 618
 619 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 620 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 621 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 622
 623 /*
 624  * For booting Linux, the board info and command line data
 625  * have to be in the first 8 MB of memory, since this is
 626  * the maximum mapped by the Linux kernel during initialization.
 627  */
 628 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 629 #define CONFIG_SYS_BOOTM_LEN    (256 << 20)     /* Increase max gunzip size */
 630
 631 #if defined(CONFIG_CMD_KGDB)
 632     #define CONFIG_KGDB_BAUDRATE        230400  /* speed to run kgdb serial port */
 633 #endif
 634
 635 /*
 636  * Environment Configuration
 637  */
 638
 639 #define CONFIG_HAS_ETH0         1
 640 #define CONFIG_HAS_ETH1         1
 641 #define CONFIG_HAS_ETH2         1
 642 #define CONFIG_HAS_ETH3         1
 643
 644 #define CONFIG_IPADDR           192.168.1.100
 645
 646 #define CONFIG_HOSTNAME         unknown
 647 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 648 #define CONFIG_BOOTFILE         "uImage"
 649 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 650
 651 #define CONFIG_SERVERIP         192.168.1.1
 652 #define CONFIG_GATEWAYIP        192.168.1.1
 653 #define CONFIG_NETMASK          255.255.255.0
 654
 655 /* default location for tftp and bootm */
 656 #define CONFIG_LOADADDR         0x10000000
 657
 658 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 659
 660 #define CONFIG_BAUDRATE 115200
 661
 662 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 663         "netdev=eth0\0"                                                 \
 664         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 665         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 666                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 667                         " +$filesize; " \
 668                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 669                         " +$filesize; " \
 670                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 671                         " $filesize; "  \
 672                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 673                         " +$filesize; " \
 674                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 675                         " $filesize\0"  \
 676         "consoledev=ttyS0\0"                                            \
 677         "ramdiskaddr=0x18000000\0"                                              \
 678         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 679         "fdtaddr=0x17c00000\0"                                          \
 680         "fdtfile=mpc8641_hpcn.dtb\0"                                    \
 681         "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"                        \
 682         "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
 683         "maxcpus=2"
 684
 685 #define CONFIG_NFSBOOTCOMMAND                                           \
 686         "setenv bootargs root=/dev/nfs rw "                             \
 687               "nfsroot=$serverip:$rootpath "                            \
 688               "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 689               "console=$consoledev,$baudrate $othbootargs;"             \
 690         "tftp $loadaddr $bootfile;"                                     \
 691         "tftp $fdtaddr $fdtfile;"                                       \
 692         "bootm $loadaddr - $fdtaddr"
 693
 694 #define CONFIG_RAMBOOTCOMMAND                                           \
 695         "setenv bootargs root=/dev/ram rw "                             \
 696               "console=$consoledev,$baudrate $othbootargs;"             \
 697         "tftp $ramdiskaddr $ramdiskfile;"                               \
 698         "tftp $loadaddr $bootfile;"                                     \
 699         "tftp $fdtaddr $fdtfile;"                                       \
 700         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 701
 702 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 703
 704 #endif  /* __CONFIG_H */