1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2006, 2010-2011 Freescale Semiconductor.
5 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
9 * MPC8641HPCN board configuration file
11 * Make sure you change the MAC address and other network params first,
12 * search for CONFIG_SERVERIP, etc. in this file.
18 /* High Level Configuration Options */
19 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
20 #define CONFIG_ADDR_MAP 1 /* Use addr map */
23 * default CCSRBAR is at 0xff700000
24 * assume U-Boot is less than 0.5MB
28 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
32 * virtual address to be used for temporary mappings. There
33 * should be 128k free at this VA.
35 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
37 #define CONFIG_SYS_SRIO
38 #define CONFIG_SRIO1 /* SRIO port 1 */
40 #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */
41 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */
42 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
43 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
45 #define CONFIG_ENV_OVERWRITE
47 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
48 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
49 #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
51 #define CONFIG_ALTIVEC 1
54 * L2CR setup -- make sure this is right for your board!
58 #define L2_ENABLE (L2CR_L2E)
60 #ifndef CONFIG_SYS_CLK_FREQ
62 extern unsigned long get_board_sys_clk(unsigned long dummy);
64 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
67 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
68 #define CONFIG_SYS_MEMTEST_END 0x00400000
71 * With the exception of PCI Memory and Rapid IO, most devices will simply
72 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
73 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
75 #ifdef CONFIG_PHYS_64BIT
76 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
78 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
82 * Base addresses -- Note these are effective addresses where the
83 * actual resources get mapped (not physical addresses)
85 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
86 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
88 /* Physical addresses */
89 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
90 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH
91 #define CONFIG_SYS_CCSRBAR_PHYS \
92 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
93 CONFIG_SYS_CCSRBAR_PHYS_HIGH)
95 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
100 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
101 #define CONFIG_DDR_SPD
103 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
104 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
106 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
107 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
108 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
109 #define CONFIG_VERY_BIG_RAM
111 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
112 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
115 * I2C addresses of SPD EEPROMs
117 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
118 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
119 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
120 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
123 * These are used when DDR doesn't use SPD.
125 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
126 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
127 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
128 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
129 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
130 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
131 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
132 #define CONFIG_SYS_DDR_MODE_1 0x00480432
133 #define CONFIG_SYS_DDR_MODE_2 0x00000000
134 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
135 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
136 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
137 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
138 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
139 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
140 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
142 #define CONFIG_ID_EEPROM
143 #define CONFIG_SYS_I2C_EEPROM_NXID
144 #define CONFIG_ID_EEPROM
145 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
146 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
148 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
149 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE
150 #define CONFIG_SYS_FLASH_BASE_PHYS \
151 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
152 CONFIG_SYS_PHYS_ADDR_HIGH)
154 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
156 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
157 | 0x00001001) /* port size 16bit */
158 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
160 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
161 | 0x00001001) /* port size 16bit */
162 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
164 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
165 | 0x00000801) /* port size 8bit */
166 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
169 * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
170 * The PIXIS and CF by themselves aren't large enough to take up the 128k
171 * required for the smallest BAT mapping, so there's a 64k hole.
173 #define CONFIG_SYS_LBC_BASE 0xffde0000
174 #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE
176 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
177 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
178 #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
179 #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
180 CONFIG_SYS_PHYS_ADDR_HIGH)
181 #define PIXIS_SIZE 0x00008000 /* 32k */
182 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
183 #define PIXIS_VER 0x1 /* Board version at offset 1 */
184 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
185 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
186 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
187 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
188 #define PIXIS_VCTL 0x10 /* VELA Control Register */
189 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
190 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
191 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
192 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
193 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
194 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
195 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
196 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
197 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
198 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
200 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
201 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
202 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
204 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
205 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
207 #undef CONFIG_SYS_FLASH_CHECKSUM
208 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
209 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
210 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
211 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
213 #define CONFIG_SYS_FLASH_EMPTY_INFO
215 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
216 #define CONFIG_SYS_RAMBOOT
218 #undef CONFIG_SYS_RAMBOOT
221 #if defined(CONFIG_SYS_RAMBOOT)
222 #undef CONFIG_SPD_EEPROM
223 #define CONFIG_SYS_SDRAM_SIZE 256
226 #undef CONFIG_CLOCKS_IN_MHZ
228 #define CONFIG_SYS_INIT_RAM_LOCK 1
229 #ifndef CONFIG_SYS_INIT_RAM_LOCK
230 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
232 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
234 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
236 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
237 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
239 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
240 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
243 #define CONFIG_SYS_NS16550_SERIAL
244 #define CONFIG_SYS_NS16550_REG_SIZE 1
245 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
247 #define CONFIG_SYS_BAUDRATE_TABLE \
248 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
250 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
251 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
256 #define CONFIG_SYS_I2C
257 #define CONFIG_SYS_I2C_FSL
258 #define CONFIG_SYS_FSL_I2C_SPEED 400000
259 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
260 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
261 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
266 #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */
267 #ifdef CONFIG_PHYS_64BIT
268 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000
269 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c
271 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE
272 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000
274 #define CONFIG_SYS_SRIO1_MEM_PHYS \
275 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
276 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
277 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
281 * Addresses are mapped 1-1.
284 #define CONFIG_SYS_PCIE1_NAME "ULI"
285 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
286 #ifdef CONFIG_PHYS_64BIT
287 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
288 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000
289 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
291 #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
292 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT
293 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
295 #define CONFIG_SYS_PCIE1_MEM_PHYS \
296 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
297 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
298 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
299 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
300 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
301 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT
302 #define CONFIG_SYS_PCIE1_IO_PHYS \
303 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
304 CONFIG_SYS_PHYS_ADDR_HIGH)
305 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
307 #ifdef CONFIG_PHYS_64BIT
309 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
310 * This will increase the amount of PCI address space available for
313 #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS
315 #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \
316 + CONFIG_SYS_PCIE1_MEM_SIZE)
318 #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \
319 + CONFIG_SYS_PCIE1_MEM_SIZE)
320 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
321 + CONFIG_SYS_PCIE1_MEM_SIZE)
322 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
323 #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \
324 + CONFIG_SYS_PCIE1_MEM_SIZE)
325 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
326 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
327 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \
328 + CONFIG_SYS_PCIE1_IO_SIZE)
329 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
330 + CONFIG_SYS_PCIE1_IO_SIZE)
331 #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \
332 + CONFIG_SYS_PCIE1_IO_SIZE)
333 #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE
335 #if defined(CONFIG_PCI)
337 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
339 #undef CONFIG_EEPRO100
342 /************************************************************
344 ************************************************************/
345 #define CONFIG_PCI_OHCI 1
346 #define CONFIG_USB_OHCI_NEW 1
347 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
348 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
349 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
351 /*PCIE video card used*/
352 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
354 /*PCI video card used*/
355 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/
359 #if defined(CONFIG_VIDEO)
360 #define CONFIG_BIOSEMU
361 #define CONFIG_ATI_RADEON_FB
362 #define CONFIG_VIDEO_LOGO
363 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
366 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
368 #ifdef CONFIG_SCSI_AHCI
369 #define CONFIG_SATA_ULI5288
370 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
371 #define CONFIG_SYS_SCSI_MAX_LUN 1
372 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
375 #endif /* CONFIG_PCI */
377 #if defined(CONFIG_TSEC_ENET)
378 #define CONFIG_TSEC1 1
379 #define CONFIG_TSEC1_NAME "eTSEC1"
380 #define CONFIG_TSEC2 1
381 #define CONFIG_TSEC2_NAME "eTSEC2"
382 #define CONFIG_TSEC3 1
383 #define CONFIG_TSEC3_NAME "eTSEC3"
384 #define CONFIG_TSEC4 1
385 #define CONFIG_TSEC4_NAME "eTSEC4"
387 #define TSEC1_PHY_ADDR 0
388 #define TSEC2_PHY_ADDR 1
389 #define TSEC3_PHY_ADDR 2
390 #define TSEC4_PHY_ADDR 3
391 #define TSEC1_PHYIDX 0
392 #define TSEC2_PHYIDX 0
393 #define TSEC3_PHYIDX 0
394 #define TSEC4_PHYIDX 0
395 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
396 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
397 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
398 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
400 #define CONFIG_ETHPRIME "eTSEC1"
402 #endif /* CONFIG_TSEC_ENET */
404 #ifdef CONFIG_PHYS_64BIT
405 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
406 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
408 /* Put physical address into the BAT format */
409 #define BAT_PHYS_ADDR(low, high) \
410 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
411 /* Convert high/low pairs to actual 64-bit value */
412 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
414 /* 32-bit systems just ignore the "high" bits */
415 #define BAT_PHYS_ADDR(low, high) (low)
416 #define PAIRED_PHYS_TO_PHYS(low, high) (low)
422 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
423 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
426 * BAT1 LBC (PIXIS/CF)
428 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
429 CONFIG_SYS_PHYS_ADDR_HIGH) \
430 | BATL_PP_RW | BATL_CACHEINHIBIT | \
432 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
434 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
435 CONFIG_SYS_PHYS_ADDR_HIGH) \
436 | BATL_PP_RW | BATL_MEMCOHERENCE)
437 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
440 * BAT2 PCIE1 and PCIE1 MEM
442 * BAT2 Rapidio Memory
445 #define CONFIG_PCI_INDIRECT_BRIDGE
446 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
447 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
448 | BATL_PP_RW | BATL_CACHEINHIBIT \
449 | BATL_GUARDEDSTORAGE)
450 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
452 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
453 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
454 | BATL_PP_RW | BATL_CACHEINHIBIT)
455 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
456 #else /* CONFIG_RIO */
457 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
458 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
459 | BATL_PP_RW | BATL_CACHEINHIBIT | \
461 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
463 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
464 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
465 | BATL_PP_RW | BATL_CACHEINHIBIT)
466 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
472 #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
473 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
474 | BATL_PP_RW | BATL_CACHEINHIBIT \
475 | BATL_GUARDEDSTORAGE)
476 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
478 #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
479 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
480 | BATL_PP_RW | BATL_CACHEINHIBIT)
481 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
483 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
484 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
485 | BATL_PP_RW | BATL_CACHEINHIBIT \
486 | BATL_GUARDEDSTORAGE)
487 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
488 | BATU_BL_1M | BATU_VS | BATU_VP)
489 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
490 | BATL_PP_RW | BATL_CACHEINHIBIT)
491 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
495 * BAT4 PCIE1_IO and PCIE2_IO
497 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
498 CONFIG_SYS_PHYS_ADDR_HIGH) \
499 | BATL_PP_RW | BATL_CACHEINHIBIT \
500 | BATL_GUARDEDSTORAGE)
501 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
503 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
504 CONFIG_SYS_PHYS_ADDR_HIGH) \
505 | BATL_PP_RW | BATL_CACHEINHIBIT)
506 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
509 * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
511 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
512 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
513 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
514 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
519 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
520 CONFIG_SYS_PHYS_ADDR_HIGH) \
521 | BATL_PP_RW | BATL_CACHEINHIBIT \
522 | BATL_GUARDEDSTORAGE)
523 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
525 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
526 CONFIG_SYS_PHYS_ADDR_HIGH) \
527 | BATL_PP_RW | BATL_MEMCOHERENCE)
528 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
530 /* Map the last 1M of flash where we're running from reset */
531 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
532 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
533 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
534 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
536 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
539 * BAT7 FREE - used later for tmp mappings
541 #define CONFIG_SYS_DBAT7L 0x00000000
542 #define CONFIG_SYS_DBAT7U 0x00000000
543 #define CONFIG_SYS_IBAT7L 0x00000000
544 #define CONFIG_SYS_IBAT7U 0x00000000
549 #ifndef CONFIG_SYS_RAMBOOT
550 #define CONFIG_ENV_ADDR \
551 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
552 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
554 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
556 #define CONFIG_ENV_SIZE 0x2000
558 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
559 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
564 #define CONFIG_BOOTP_BOOTFILESIZE
566 #undef CONFIG_WATCHDOG /* watchdog disabled */
569 * Miscellaneous configurable options
571 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
574 * For booting Linux, the board info and command line data
575 * have to be in the first 8 MB of memory, since this is
576 * the maximum mapped by the Linux kernel during initialization.
578 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
579 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */
581 #if defined(CONFIG_CMD_KGDB)
582 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
586 * Environment Configuration
589 #define CONFIG_HAS_ETH0 1
590 #define CONFIG_HAS_ETH1 1
591 #define CONFIG_HAS_ETH2 1
592 #define CONFIG_HAS_ETH3 1
594 #define CONFIG_IPADDR 192.168.1.100
596 #define CONFIG_HOSTNAME "unknown"
597 #define CONFIG_ROOTPATH "/opt/nfsroot"
598 #define CONFIG_BOOTFILE "uImage"
599 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
601 #define CONFIG_SERVERIP 192.168.1.1
602 #define CONFIG_GATEWAYIP 192.168.1.1
603 #define CONFIG_NETMASK 255.255.255.0
605 /* default location for tftp and bootm */
606 #define CONFIG_LOADADDR 0x10000000
608 #define CONFIG_EXTRA_ENV_SETTINGS \
610 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
611 "tftpflash=tftpboot $loadaddr $uboot; " \
612 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
614 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
616 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
618 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
620 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
622 "consoledev=ttyS0\0" \
623 "ramdiskaddr=0x18000000\0" \
624 "ramdiskfile=your.ramdisk.u-boot\0" \
625 "fdtaddr=0x17c00000\0" \
626 "fdtfile=mpc8641_hpcn.dtb\0" \
627 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
628 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
631 #define CONFIG_NFSBOOTCOMMAND \
632 "setenv bootargs root=/dev/nfs rw " \
633 "nfsroot=$serverip:$rootpath " \
634 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
635 "console=$consoledev,$baudrate $othbootargs;" \
636 "tftp $loadaddr $bootfile;" \
637 "tftp $fdtaddr $fdtfile;" \
638 "bootm $loadaddr - $fdtaddr"
640 #define CONFIG_RAMBOOTCOMMAND \
641 "setenv bootargs root=/dev/ram rw " \
642 "console=$consoledev,$baudrate $othbootargs;" \
643 "tftp $ramdiskaddr $ramdiskfile;" \
644 "tftp $loadaddr $bootfile;" \
645 "tftp $fdtaddr $fdtfile;" \
646 "bootm $loadaddr $ramdiskaddr $fdtaddr"
648 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
650 #endif /* __CONFIG_H */