1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2006, 2010-2011 Freescale Semiconductor.
5 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
9 * MPC8641HPCN board configuration file
11 * Make sure you change the MAC address and other network params first,
12 * search for CONFIG_SERVERIP, etc. in this file.
18 /* High Level Configuration Options */
19 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
20 #define CONFIG_ADDR_MAP 1 /* Use addr map */
23 * default CCSRBAR is at 0xff700000
24 * assume U-Boot is less than 0.5MB
28 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
32 * virtual address to be used for temporary mappings. There
33 * should be 128k free at this VA.
35 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
37 #define CONFIG_SYS_SRIO
38 #define CONFIG_SRIO1 /* SRIO port 1 */
40 #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */
41 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */
42 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
43 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
45 #define CONFIG_ENV_OVERWRITE
47 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
48 #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
50 #define CONFIG_ALTIVEC 1
53 * L2CR setup -- make sure this is right for your board!
57 #define L2_ENABLE (L2CR_L2E)
59 #ifndef CONFIG_SYS_CLK_FREQ
61 extern unsigned long get_board_sys_clk(unsigned long dummy);
63 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
66 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
67 #define CONFIG_SYS_MEMTEST_END 0x00400000
70 * With the exception of PCI Memory and Rapid IO, most devices will simply
71 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
72 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
74 #ifdef CONFIG_PHYS_64BIT
75 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
77 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
81 * Base addresses -- Note these are effective addresses where the
82 * actual resources get mapped (not physical addresses)
84 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
85 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
87 /* Physical addresses */
88 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
89 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH
90 #define CONFIG_SYS_CCSRBAR_PHYS \
91 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
92 CONFIG_SYS_CCSRBAR_PHYS_HIGH)
94 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
99 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
100 #define CONFIG_DDR_SPD
102 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
103 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
105 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
106 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
107 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
108 #define CONFIG_VERY_BIG_RAM
110 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
111 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
114 * I2C addresses of SPD EEPROMs
116 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
117 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
118 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
119 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
122 * These are used when DDR doesn't use SPD.
124 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
125 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
126 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
127 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
128 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
129 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
130 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
131 #define CONFIG_SYS_DDR_MODE_1 0x00480432
132 #define CONFIG_SYS_DDR_MODE_2 0x00000000
133 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
134 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
135 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
136 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
137 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
138 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
139 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
141 #define CONFIG_ID_EEPROM
142 #define CONFIG_SYS_I2C_EEPROM_NXID
143 #define CONFIG_ID_EEPROM
144 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
145 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
147 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
148 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE
149 #define CONFIG_SYS_FLASH_BASE_PHYS \
150 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
151 CONFIG_SYS_PHYS_ADDR_HIGH)
153 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
155 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
156 | 0x00001001) /* port size 16bit */
157 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
159 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
160 | 0x00001001) /* port size 16bit */
161 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
163 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
164 | 0x00000801) /* port size 8bit */
165 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
168 * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
169 * The PIXIS and CF by themselves aren't large enough to take up the 128k
170 * required for the smallest BAT mapping, so there's a 64k hole.
172 #define CONFIG_SYS_LBC_BASE 0xffde0000
173 #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE
175 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
176 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
177 #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
178 #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
179 CONFIG_SYS_PHYS_ADDR_HIGH)
180 #define PIXIS_SIZE 0x00008000 /* 32k */
181 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
182 #define PIXIS_VER 0x1 /* Board version at offset 1 */
183 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
184 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
185 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
186 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
187 #define PIXIS_VCTL 0x10 /* VELA Control Register */
188 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
189 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
190 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
191 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
192 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
193 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
194 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
195 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
196 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
197 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
199 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
200 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
201 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
203 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
204 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
206 #undef CONFIG_SYS_FLASH_CHECKSUM
207 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
208 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
209 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
210 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
212 #define CONFIG_SYS_FLASH_EMPTY_INFO
214 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
215 #define CONFIG_SYS_RAMBOOT
217 #undef CONFIG_SYS_RAMBOOT
220 #if defined(CONFIG_SYS_RAMBOOT)
221 #undef CONFIG_SPD_EEPROM
222 #define CONFIG_SYS_SDRAM_SIZE 256
225 #undef CONFIG_CLOCKS_IN_MHZ
227 #define CONFIG_SYS_INIT_RAM_LOCK 1
228 #ifndef CONFIG_SYS_INIT_RAM_LOCK
229 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
231 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
233 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
235 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
236 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
238 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
239 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
242 #define CONFIG_SYS_NS16550_SERIAL
243 #define CONFIG_SYS_NS16550_REG_SIZE 1
244 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
246 #define CONFIG_SYS_BAUDRATE_TABLE \
247 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
249 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
250 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
255 #define CONFIG_SYS_I2C
256 #define CONFIG_SYS_I2C_FSL
257 #define CONFIG_SYS_FSL_I2C_SPEED 400000
258 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
259 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
260 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
265 #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */
266 #ifdef CONFIG_PHYS_64BIT
267 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000
268 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c
270 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE
271 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000
273 #define CONFIG_SYS_SRIO1_MEM_PHYS \
274 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
275 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
276 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
280 * Addresses are mapped 1-1.
283 #define CONFIG_SYS_PCIE1_NAME "ULI"
284 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
285 #ifdef CONFIG_PHYS_64BIT
286 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
287 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000
288 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
290 #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
291 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT
292 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
294 #define CONFIG_SYS_PCIE1_MEM_PHYS \
295 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
296 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
297 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
298 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
299 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
300 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT
301 #define CONFIG_SYS_PCIE1_IO_PHYS \
302 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
303 CONFIG_SYS_PHYS_ADDR_HIGH)
304 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
306 #ifdef CONFIG_PHYS_64BIT
308 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
309 * This will increase the amount of PCI address space available for
312 #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS
314 #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \
315 + CONFIG_SYS_PCIE1_MEM_SIZE)
317 #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \
318 + CONFIG_SYS_PCIE1_MEM_SIZE)
319 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
320 + CONFIG_SYS_PCIE1_MEM_SIZE)
321 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
322 #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \
323 + CONFIG_SYS_PCIE1_MEM_SIZE)
324 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
325 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
326 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \
327 + CONFIG_SYS_PCIE1_IO_SIZE)
328 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
329 + CONFIG_SYS_PCIE1_IO_SIZE)
330 #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \
331 + CONFIG_SYS_PCIE1_IO_SIZE)
332 #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE
334 #if defined(CONFIG_PCI)
336 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
338 #undef CONFIG_EEPRO100
341 /************************************************************
343 ************************************************************/
344 #define CONFIG_PCI_OHCI 1
345 #define CONFIG_USB_OHCI_NEW 1
346 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
347 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
348 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
350 /*PCIE video card used*/
351 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
353 /*PCI video card used*/
354 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/
358 #if defined(CONFIG_VIDEO)
359 #define CONFIG_BIOSEMU
360 #define CONFIG_ATI_RADEON_FB
361 #define CONFIG_VIDEO_LOGO
362 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
365 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
367 #ifdef CONFIG_SCSI_AHCI
368 #define CONFIG_SATA_ULI5288
369 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
370 #define CONFIG_SYS_SCSI_MAX_LUN 1
371 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
374 #endif /* CONFIG_PCI */
376 #if defined(CONFIG_TSEC_ENET)
377 #define CONFIG_TSEC1 1
378 #define CONFIG_TSEC1_NAME "eTSEC1"
379 #define CONFIG_TSEC2 1
380 #define CONFIG_TSEC2_NAME "eTSEC2"
381 #define CONFIG_TSEC3 1
382 #define CONFIG_TSEC3_NAME "eTSEC3"
383 #define CONFIG_TSEC4 1
384 #define CONFIG_TSEC4_NAME "eTSEC4"
386 #define TSEC1_PHY_ADDR 0
387 #define TSEC2_PHY_ADDR 1
388 #define TSEC3_PHY_ADDR 2
389 #define TSEC4_PHY_ADDR 3
390 #define TSEC1_PHYIDX 0
391 #define TSEC2_PHYIDX 0
392 #define TSEC3_PHYIDX 0
393 #define TSEC4_PHYIDX 0
394 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
395 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
396 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
397 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
399 #define CONFIG_ETHPRIME "eTSEC1"
401 #endif /* CONFIG_TSEC_ENET */
403 #ifdef CONFIG_PHYS_64BIT
404 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
405 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
407 /* Put physical address into the BAT format */
408 #define BAT_PHYS_ADDR(low, high) \
409 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
410 /* Convert high/low pairs to actual 64-bit value */
411 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
413 /* 32-bit systems just ignore the "high" bits */
414 #define BAT_PHYS_ADDR(low, high) (low)
415 #define PAIRED_PHYS_TO_PHYS(low, high) (low)
421 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
422 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
425 * BAT1 LBC (PIXIS/CF)
427 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
428 CONFIG_SYS_PHYS_ADDR_HIGH) \
429 | BATL_PP_RW | BATL_CACHEINHIBIT | \
431 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
433 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
434 CONFIG_SYS_PHYS_ADDR_HIGH) \
435 | BATL_PP_RW | BATL_MEMCOHERENCE)
436 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
439 * BAT2 PCIE1 and PCIE1 MEM
441 * BAT2 Rapidio Memory
444 #define CONFIG_PCI_INDIRECT_BRIDGE
445 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
446 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
447 | BATL_PP_RW | BATL_CACHEINHIBIT \
448 | BATL_GUARDEDSTORAGE)
449 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
451 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
452 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
453 | BATL_PP_RW | BATL_CACHEINHIBIT)
454 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
455 #else /* CONFIG_RIO */
456 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
457 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
458 | BATL_PP_RW | BATL_CACHEINHIBIT | \
460 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
462 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
463 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
464 | BATL_PP_RW | BATL_CACHEINHIBIT)
465 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
471 #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
472 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
473 | BATL_PP_RW | BATL_CACHEINHIBIT \
474 | BATL_GUARDEDSTORAGE)
475 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
477 #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
478 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
479 | BATL_PP_RW | BATL_CACHEINHIBIT)
480 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
482 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
483 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
484 | BATL_PP_RW | BATL_CACHEINHIBIT \
485 | BATL_GUARDEDSTORAGE)
486 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
487 | BATU_BL_1M | BATU_VS | BATU_VP)
488 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
489 | BATL_PP_RW | BATL_CACHEINHIBIT)
490 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
494 * BAT4 PCIE1_IO and PCIE2_IO
496 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
497 CONFIG_SYS_PHYS_ADDR_HIGH) \
498 | BATL_PP_RW | BATL_CACHEINHIBIT \
499 | BATL_GUARDEDSTORAGE)
500 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
502 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
503 CONFIG_SYS_PHYS_ADDR_HIGH) \
504 | BATL_PP_RW | BATL_CACHEINHIBIT)
505 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
508 * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
510 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
511 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
512 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
513 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
518 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
519 CONFIG_SYS_PHYS_ADDR_HIGH) \
520 | BATL_PP_RW | BATL_CACHEINHIBIT \
521 | BATL_GUARDEDSTORAGE)
522 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
524 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
525 CONFIG_SYS_PHYS_ADDR_HIGH) \
526 | BATL_PP_RW | BATL_MEMCOHERENCE)
527 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
529 /* Map the last 1M of flash where we're running from reset */
530 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
531 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
532 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
533 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
535 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
538 * BAT7 FREE - used later for tmp mappings
540 #define CONFIG_SYS_DBAT7L 0x00000000
541 #define CONFIG_SYS_DBAT7U 0x00000000
542 #define CONFIG_SYS_IBAT7L 0x00000000
543 #define CONFIG_SYS_IBAT7U 0x00000000
548 #ifndef CONFIG_SYS_RAMBOOT
549 #define CONFIG_ENV_ADDR \
550 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
551 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
553 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
555 #define CONFIG_ENV_SIZE 0x2000
557 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
558 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
563 #define CONFIG_BOOTP_BOOTFILESIZE
565 #undef CONFIG_WATCHDOG /* watchdog disabled */
568 * Miscellaneous configurable options
570 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
573 * For booting Linux, the board info and command line data
574 * have to be in the first 8 MB of memory, since this is
575 * the maximum mapped by the Linux kernel during initialization.
577 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
578 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */
580 #if defined(CONFIG_CMD_KGDB)
581 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
585 * Environment Configuration
588 #define CONFIG_HAS_ETH0 1
589 #define CONFIG_HAS_ETH1 1
590 #define CONFIG_HAS_ETH2 1
591 #define CONFIG_HAS_ETH3 1
593 #define CONFIG_IPADDR 192.168.1.100
595 #define CONFIG_HOSTNAME "unknown"
596 #define CONFIG_ROOTPATH "/opt/nfsroot"
597 #define CONFIG_BOOTFILE "uImage"
598 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
600 #define CONFIG_SERVERIP 192.168.1.1
601 #define CONFIG_GATEWAYIP 192.168.1.1
602 #define CONFIG_NETMASK 255.255.255.0
604 /* default location for tftp and bootm */
605 #define CONFIG_LOADADDR 0x10000000
607 #define CONFIG_EXTRA_ENV_SETTINGS \
609 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
610 "tftpflash=tftpboot $loadaddr $uboot; " \
611 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
613 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
615 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
617 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
619 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
621 "consoledev=ttyS0\0" \
622 "ramdiskaddr=0x18000000\0" \
623 "ramdiskfile=your.ramdisk.u-boot\0" \
624 "fdtaddr=0x17c00000\0" \
625 "fdtfile=mpc8641_hpcn.dtb\0" \
626 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
627 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
630 #define CONFIG_NFSBOOTCOMMAND \
631 "setenv bootargs root=/dev/nfs rw " \
632 "nfsroot=$serverip:$rootpath " \
633 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
634 "console=$consoledev,$baudrate $othbootargs;" \
635 "tftp $loadaddr $bootfile;" \
636 "tftp $fdtaddr $fdtfile;" \
637 "bootm $loadaddr - $fdtaddr"
639 #define CONFIG_RAMBOOTCOMMAND \
640 "setenv bootargs root=/dev/ram rw " \
641 "console=$consoledev,$baudrate $othbootargs;" \
642 "tftp $ramdiskaddr $ramdiskfile;" \
643 "tftp $loadaddr $bootfile;" \
644 "tftp $fdtaddr $fdtfile;" \
645 "bootm $loadaddr $ramdiskaddr $fdtaddr"
647 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
649 #endif /* __CONFIG_H */