2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
8 * MPC8610HPCD board configuration file
14 /* High Level Configuration Options */
15 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
17 #define CONFIG_SYS_TEXT_BASE 0xfff00000
20 #define CONFIG_FSL_DIU_FB
22 #ifdef CONFIG_FSL_DIU_FB
23 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
24 #define CONFIG_CMD_BMP
25 #define CONFIG_VIDEO_LOGO
26 #define CONFIG_VIDEO_BMP_LOGO
30 #define CONFIG_SYS_DIAG_ADDR 0xff800000
34 * virtual address to be used for temporary mappings. There
35 * should be 128k free at this VA.
37 #define CONFIG_SYS_SCRATCH_VA 0xc0000000
39 #define CONFIG_PCI1 1 /* PCI controller 1 */
40 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
41 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
42 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
43 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
44 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
46 #define CONFIG_ENV_OVERWRITE
47 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
49 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
50 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */
51 #define CONFIG_ALTIVEC 1
54 * L2CR setup -- make sure this is right for your board!
58 #define L2_ENABLE (L2CR_L2E |0x00100000 )
60 #ifndef CONFIG_SYS_CLK_FREQ
61 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
64 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
65 #define CONFIG_MISC_INIT_R 1
67 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
68 #define CONFIG_SYS_MEMTEST_END 0x00400000
71 * Base addresses -- Note these are effective addresses where the
72 * actual resources get mapped (not physical addresses)
74 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
75 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
77 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
78 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
79 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
82 #undef CONFIG_FSL_DDR_INTERACTIVE
83 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */
84 #define CONFIG_DDR_SPD
86 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
87 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
89 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
90 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
91 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
92 #define CONFIG_VERY_BIG_RAM
94 #define CONFIG_NUM_DDR_CONTROLLERS 1
95 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
96 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
98 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
100 /* These are used when DDR doesn't use SPD. */
101 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
104 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
105 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
106 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
107 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
108 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
109 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
110 #define CONFIG_SYS_DDR_MODE_1 0x00480432
111 #define CONFIG_SYS_DDR_MODE_2 0x00000000
112 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
113 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
114 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
115 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
116 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
117 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
118 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
120 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
121 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
122 #define CONFIG_SYS_DDR_SBE 0x000f0000
126 #define CONFIG_ID_EEPROM
127 #define CONFIG_SYS_I2C_EEPROM_NXID
128 #define CONFIG_ID_EEPROM
129 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
130 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
132 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
133 #define CONFIG_SYS_FLASH_BASE2 0xf8000000
135 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
137 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */
138 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/
140 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */
141 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */
143 #define CONFIG_SYS_BR2_PRELIM 0xf0000000
144 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */
146 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */
147 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
149 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
150 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */
151 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
152 #define PIXIS_VER 0x1 /* Board version at offset 1 */
153 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
154 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
155 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */
156 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
157 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/
158 #define PIXIS_VCTL 0x10 /* VELA Control Register */
159 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
160 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
161 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
162 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
163 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
164 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
165 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
166 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */
168 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
169 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
171 #undef CONFIG_SYS_FLASH_CHECKSUM
172 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
173 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
174 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
175 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
177 #define CONFIG_FLASH_CFI_DRIVER
178 #define CONFIG_SYS_FLASH_CFI
179 #define CONFIG_SYS_FLASH_EMPTY_INFO
181 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
182 #define CONFIG_SYS_RAMBOOT
184 #undef CONFIG_SYS_RAMBOOT
187 #if defined(CONFIG_SYS_RAMBOOT)
188 #undef CONFIG_SPD_EEPROM
189 #define CONFIG_SYS_SDRAM_SIZE 256
192 #undef CONFIG_CLOCKS_IN_MHZ
194 #define CONFIG_SYS_INIT_RAM_LOCK 1
195 #ifndef CONFIG_SYS_INIT_RAM_LOCK
196 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
198 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */
200 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
202 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
203 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
205 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
206 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
209 #define CONFIG_CONS_INDEX 1
210 #define CONFIG_SYS_NS16550_SERIAL
211 #define CONFIG_SYS_NS16550_REG_SIZE 1
212 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
214 #define CONFIG_SYS_BAUDRATE_TABLE \
215 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
217 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
218 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
220 /* maximum size of the flat tree (8K) */
221 #define OF_FLAT_TREE_MAX_SIZE 8192
226 #define CONFIG_SYS_I2C
227 #define CONFIG_SYS_I2C_FSL
228 #define CONFIG_SYS_FSL_I2C_SPEED 400000
229 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
230 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
231 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
235 * Addresses are mapped 1-1.
237 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
238 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
239 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
240 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
241 #define CONFIG_SYS_PCI1_IO_BUS 0x0000000
242 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
243 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
244 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
246 /* controller 1, Base address 0xa000 */
247 #define CONFIG_SYS_PCIE1_NAME "ULI"
248 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
249 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
250 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
251 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
252 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
253 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
255 /* controller 2, Base Address 0x9000 */
256 #define CONFIG_SYS_PCIE2_NAME "Slot 1"
257 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
258 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
259 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
260 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */
261 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
262 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */
264 #if defined(CONFIG_PCI)
266 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
268 #define CONFIG_CMD_REGINFO
270 #define CONFIG_ULI526X
271 #ifdef CONFIG_ULI526X
274 /************************************************************
276 ************************************************************/
277 #define CONFIG_PCI_OHCI 1
278 #define CONFIG_USB_OHCI_NEW 1
279 #define CONFIG_SYS_USB_EVENT_POLL 1
280 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
281 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
282 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
284 #if !defined(CONFIG_PCI_PNP)
285 #define PCI_ENET0_IOADDR 0xe0000000
286 #define PCI_ENET0_MEMADDR 0xe0000000
287 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
290 #define CONFIG_DOS_PARTITION
291 #define CONFIG_SCSI_AHCI
293 #ifdef CONFIG_SCSI_AHCI
294 #define CONFIG_LIBATA
295 #define CONFIG_SATA_ULI5288
296 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
297 #define CONFIG_SYS_SCSI_MAX_LUN 1
298 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
299 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
302 #endif /* CONFIG_PCI */
305 * BAT0 2G Cacheable, non-guarded
308 #define CONFIG_SYS_DBAT0L (BATL_PP_RW)
309 #define CONFIG_SYS_IBAT0L (BATL_PP_RW)
312 * BAT1 1G Cache-inhibited, guarded
313 * 0x8000_0000 256M PCI-1 Memory
314 * 0xa000_0000 256M PCI-Express 1 Memory
315 * 0x9000_0000 256M PCI-Express 2 Memory
318 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
319 | BATL_GUARDEDSTORAGE)
320 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
321 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
322 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
325 * BAT2 16M Cache-inhibited, guarded
326 * 0xe100_0000 1M PCI-1 I/O
329 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
330 | BATL_GUARDEDSTORAGE)
331 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
332 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
333 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
336 * BAT3 4M Cache-inhibited, guarded
337 * 0xe000_0000 4M CCSR
340 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
341 | BATL_GUARDEDSTORAGE)
342 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
343 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
344 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
346 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
347 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
348 | BATL_PP_RW | BATL_CACHEINHIBIT \
349 | BATL_GUARDEDSTORAGE)
350 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
351 | BATU_BL_1M | BATU_VS | BATU_VP)
352 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
353 | BATL_PP_RW | BATL_CACHEINHIBIT)
354 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
358 * BAT4 32M Cache-inhibited, guarded
359 * 0xe200_0000 1M PCI-Express 2 I/O
360 * 0xe300_0000 1M PCI-Express 1 I/O
363 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
364 | BATL_GUARDEDSTORAGE)
365 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
366 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
367 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
370 * BAT5 128K Cacheable, non-guarded
371 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
373 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
374 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
375 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
376 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
379 * BAT6 256M Cache-inhibited, guarded
380 * 0xf000_0000 256M FLASH
382 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
383 | BATL_GUARDEDSTORAGE)
384 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
385 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
386 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
388 /* Map the last 1M of flash where we're running from reset */
389 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
390 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
391 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
392 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
394 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
397 * BAT7 4M Cache-inhibited, guarded
398 * 0xe800_0000 4M PIXIS
400 #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
401 | BATL_GUARDEDSTORAGE)
402 #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
403 #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
404 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
409 #ifndef CONFIG_SYS_RAMBOOT
410 #define CONFIG_ENV_IS_IN_FLASH 1
411 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
412 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */
413 #define CONFIG_ENV_SIZE 0x2000
415 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
416 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
417 #define CONFIG_ENV_SIZE 0x2000
420 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
421 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
426 #define CONFIG_BOOTP_BOOTFILESIZE
427 #define CONFIG_BOOTP_BOOTPATH
428 #define CONFIG_BOOTP_GATEWAY
429 #define CONFIG_BOOTP_HOSTNAME
432 * Command line configuration.
435 #if defined(CONFIG_PCI)
436 #define CONFIG_CMD_PCI
440 #define CONFIG_WATCHDOG /* watchdog enabled */
441 #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
444 * Miscellaneous configurable options
446 #define CONFIG_SYS_LONGHELP /* undef to save memory */
447 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
448 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
450 #if defined(CONFIG_CMD_KGDB)
451 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
453 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
456 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
457 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
458 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
461 * For booting Linux, the board info and command line data
462 * have to be in the first 8 MB of memory, since this is
463 * the maximum mapped by the Linux kernel during initialization.
465 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
466 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */
468 #if defined(CONFIG_CMD_KGDB)
469 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
473 * Environment Configuration
475 #define CONFIG_IPADDR 192.168.1.100
477 #define CONFIG_HOSTNAME unknown
478 #define CONFIG_ROOTPATH "/opt/nfsroot"
479 #define CONFIG_BOOTFILE "uImage"
480 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin
482 #define CONFIG_SERVERIP 192.168.1.1
483 #define CONFIG_GATEWAYIP 192.168.1.1
484 #define CONFIG_NETMASK 255.255.255.0
486 /* default location for tftp and bootm */
487 #define CONFIG_LOADADDR 0x10000000
489 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
491 #define CONFIG_BAUDRATE 115200
493 #if defined(CONFIG_PCI1)
495 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
496 "echo e;md ${a}e00 9\0" \
497 "pci1regs=setenv a e0008; run pcireg\0" \
498 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
499 "pci d.w $b.0 56 1\0" \
500 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
501 "pci w.w $b.0 56 ffff\0" \
502 "pci1err=setenv a e0008; run pcierr\0" \
503 "pci1errc=setenv a e0008; run pcierrc\0"
508 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
510 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
511 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
512 "pcie1regs=setenv a e000a; run pciereg\0" \
513 "pcie2regs=setenv a e0009; run pciereg\0" \
514 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
515 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
516 "pci d $b.0 130 1\0" \
517 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
518 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
519 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
520 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
521 "pcie1err=setenv a e000a; run pcieerr\0" \
522 "pcie2err=setenv a e0009; run pcieerr\0" \
523 "pcie1errc=setenv a e000a; run pcieerrc\0" \
524 "pcie2errc=setenv a e0009; run pcieerrc\0"
530 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
531 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
532 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
533 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
534 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
535 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
536 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
537 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
540 #define CONFIG_EXTRA_ENV_SETTINGS \
542 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
543 "tftpflash=tftpboot $loadaddr $uboot; " \
544 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
546 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
548 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
550 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
552 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
554 "consoledev=ttyS0\0" \
555 "ramdiskaddr=0x18000000\0" \
556 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
557 "fdtaddr=0x17c00000\0" \
558 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
560 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
561 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
563 "eoi=mw e00400b0 0\0" \
564 "iack=md e00400a0 1\0" \
565 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
566 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
568 "ddr1regs=setenv a e0002; run ddrreg\0" \
569 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
570 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
571 "md ${a}e60 1; md ${a}ef0 1d\0" \
572 "guregs=setenv a e00e0; run gureg\0" \
573 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
574 "mcmregs=setenv a e0001; run mcmreg\0" \
575 "diuregs=md e002c000 1d\0" \
576 "dium=mw e002c01c\0" \
577 "diuerr=md e002c014 1\0" \
578 "pmregs=md e00e1000 2b\0" \
579 "lawregs=md e0000c08 4b\0" \
580 "lbcregs=md e0005000 36\0" \
581 "dma0regs=md e0021100 12\0" \
582 "dma1regs=md e0021180 12\0" \
583 "dma2regs=md e0021200 12\0" \
584 "dma3regs=md e0021280 12\0" \
589 #define CONFIG_EXTRA_ENV_SETTINGS \
591 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
592 "consoledev=ttyS0\0" \
593 "ramdiskaddr=0x18000000\0" \
594 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
595 "fdtaddr=0x17c00000\0" \
596 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
600 #define CONFIG_NFSBOOTCOMMAND \
601 "setenv bootargs root=/dev/nfs rw " \
602 "nfsroot=$serverip:$rootpath " \
603 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
604 "console=$consoledev,$baudrate $othbootargs;" \
605 "tftp $loadaddr $bootfile;" \
606 "tftp $fdtaddr $fdtfile;" \
607 "bootm $loadaddr - $fdtaddr"
609 #define CONFIG_RAMBOOTCOMMAND \
610 "setenv bootargs root=/dev/ram rw " \
611 "console=$consoledev,$baudrate $othbootargs;" \
612 "tftp $ramdiskaddr $ramdiskfile;" \
613 "tftp $loadaddr $bootfile;" \
614 "tftp $fdtaddr $fdtfile;" \
615 "bootm $loadaddr $ramdiskaddr $fdtaddr"
617 #define CONFIG_BOOTCOMMAND \
618 "setenv bootargs root=/dev/$bdev rw " \
619 "console=$consoledev,$baudrate $othbootargs;" \
620 "tftp $loadaddr $bootfile;" \
621 "tftp $fdtaddr $fdtfile;" \
622 "bootm $loadaddr - $fdtaddr"
624 #endif /* __CONFIG_H */