2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
8 * MPC8610HPCD board configuration file
14 /* High Level Configuration Options */
15 #define CONFIG_MPC8610 1 /* MPC8610 specific */
16 #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */
17 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
19 #define CONFIG_SYS_TEXT_BASE 0xfff00000
22 #define CONFIG_FSL_DIU_FB
24 #ifdef CONFIG_FSL_DIU_FB
25 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
26 #define CONFIG_CMD_BMP
27 #define CONFIG_VIDEO_LOGO
28 #define CONFIG_VIDEO_BMP_LOGO
32 #define CONFIG_SYS_DIAG_ADDR 0xff800000
36 * virtual address to be used for temporary mappings. There
37 * should be 128k free at this VA.
39 #define CONFIG_SYS_SCRATCH_VA 0xc0000000
41 #define CONFIG_PCI 1 /* Enable PCI/PCIE*/
42 #define CONFIG_PCI1 1 /* PCI controller 1 */
43 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
44 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
45 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
46 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
47 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
48 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
50 #define CONFIG_ENV_OVERWRITE
51 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
53 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
54 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */
55 #define CONFIG_ALTIVEC 1
58 * L2CR setup -- make sure this is right for your board!
62 #define L2_ENABLE (L2CR_L2E |0x00100000 )
64 #ifndef CONFIG_SYS_CLK_FREQ
65 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
68 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
69 #define CONFIG_MISC_INIT_R 1
71 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
72 #define CONFIG_SYS_MEMTEST_END 0x00400000
75 * Base addresses -- Note these are effective addresses where the
76 * actual resources get mapped (not physical addresses)
78 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
79 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
80 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
82 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
83 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
84 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
87 #define CONFIG_SYS_FSL_DDR2
88 #undef CONFIG_FSL_DDR_INTERACTIVE
89 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */
90 #define CONFIG_DDR_SPD
92 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
93 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
95 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
96 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
97 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
98 #define CONFIG_VERY_BIG_RAM
100 #define CONFIG_NUM_DDR_CONTROLLERS 1
101 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
102 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
104 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
106 /* These are used when DDR doesn't use SPD. */
107 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
110 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
111 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
112 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
113 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
114 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
115 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
116 #define CONFIG_SYS_DDR_MODE_1 0x00480432
117 #define CONFIG_SYS_DDR_MODE_2 0x00000000
118 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
119 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
120 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
121 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
122 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
123 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
124 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
126 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
127 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
128 #define CONFIG_SYS_DDR_SBE 0x000f0000
132 #define CONFIG_ID_EEPROM
133 #define CONFIG_SYS_I2C_EEPROM_NXID
134 #define CONFIG_ID_EEPROM
135 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
136 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
138 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
139 #define CONFIG_SYS_FLASH_BASE2 0xf8000000
141 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
143 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */
144 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/
146 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */
147 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */
149 #define CONFIG_SYS_BR2_PRELIM 0xf0000000
150 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */
152 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */
153 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
155 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
156 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */
157 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
158 #define PIXIS_VER 0x1 /* Board version at offset 1 */
159 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
160 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
161 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */
162 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
163 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/
164 #define PIXIS_VCTL 0x10 /* VELA Control Register */
165 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
166 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
167 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
168 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
169 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
170 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
171 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
172 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */
174 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
175 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
177 #undef CONFIG_SYS_FLASH_CHECKSUM
178 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
179 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
180 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
181 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
183 #define CONFIG_FLASH_CFI_DRIVER
184 #define CONFIG_SYS_FLASH_CFI
185 #define CONFIG_SYS_FLASH_EMPTY_INFO
187 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
188 #define CONFIG_SYS_RAMBOOT
190 #undef CONFIG_SYS_RAMBOOT
193 #if defined(CONFIG_SYS_RAMBOOT)
194 #undef CONFIG_SPD_EEPROM
195 #define CONFIG_SYS_SDRAM_SIZE 256
198 #undef CONFIG_CLOCKS_IN_MHZ
200 #define CONFIG_SYS_INIT_RAM_LOCK 1
201 #ifndef CONFIG_SYS_INIT_RAM_LOCK
202 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
204 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */
206 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
208 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
209 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
211 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
212 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
215 #define CONFIG_CONS_INDEX 1
216 #define CONFIG_SYS_NS16550_SERIAL
217 #define CONFIG_SYS_NS16550_REG_SIZE 1
218 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
220 #define CONFIG_SYS_BAUDRATE_TABLE \
221 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
223 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
224 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
226 /* maximum size of the flat tree (8K) */
227 #define OF_FLAT_TREE_MAX_SIZE 8192
232 #define CONFIG_SYS_I2C
233 #define CONFIG_SYS_I2C_FSL
234 #define CONFIG_SYS_FSL_I2C_SPEED 400000
235 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
236 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
237 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
241 * Addresses are mapped 1-1.
243 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
244 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
245 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
246 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
247 #define CONFIG_SYS_PCI1_IO_BUS 0x0000000
248 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
249 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
250 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
252 /* controller 1, Base address 0xa000 */
253 #define CONFIG_SYS_PCIE1_NAME "ULI"
254 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
255 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
256 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
257 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
258 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
259 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
261 /* controller 2, Base Address 0x9000 */
262 #define CONFIG_SYS_PCIE2_NAME "Slot 1"
263 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
264 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
265 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
266 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */
267 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
268 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */
270 #if defined(CONFIG_PCI)
272 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
274 #define CONFIG_PCI_PNP /* do pci plug-and-play */
275 #define CONFIG_CMD_REGINFO
277 #define CONFIG_ULI526X
278 #ifdef CONFIG_ULI526X
281 /************************************************************
283 ************************************************************/
284 #define CONFIG_PCI_OHCI 1
285 #define CONFIG_USB_OHCI_NEW 1
286 #define CONFIG_USB_KEYBOARD 1
287 #define CONFIG_SYS_STDIO_DEREGISTER
288 #define CONFIG_SYS_USB_EVENT_POLL 1
289 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
290 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
291 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
293 #if !defined(CONFIG_PCI_PNP)
294 #define PCI_ENET0_IOADDR 0xe0000000
295 #define PCI_ENET0_MEMADDR 0xe0000000
296 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
299 #define CONFIG_DOS_PARTITION
300 #define CONFIG_SCSI_AHCI
302 #ifdef CONFIG_SCSI_AHCI
303 #define CONFIG_LIBATA
304 #define CONFIG_SATA_ULI5288
305 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
306 #define CONFIG_SYS_SCSI_MAX_LUN 1
307 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
308 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
311 #endif /* CONFIG_PCI */
314 * BAT0 2G Cacheable, non-guarded
317 #define CONFIG_SYS_DBAT0L (BATL_PP_RW)
318 #define CONFIG_SYS_IBAT0L (BATL_PP_RW)
321 * BAT1 1G Cache-inhibited, guarded
322 * 0x8000_0000 256M PCI-1 Memory
323 * 0xa000_0000 256M PCI-Express 1 Memory
324 * 0x9000_0000 256M PCI-Express 2 Memory
327 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
328 | BATL_GUARDEDSTORAGE)
329 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
330 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
331 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
334 * BAT2 16M Cache-inhibited, guarded
335 * 0xe100_0000 1M PCI-1 I/O
338 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
339 | BATL_GUARDEDSTORAGE)
340 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
341 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
342 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
345 * BAT3 4M Cache-inhibited, guarded
346 * 0xe000_0000 4M CCSR
349 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
350 | BATL_GUARDEDSTORAGE)
351 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
352 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
353 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
355 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
356 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
357 | BATL_PP_RW | BATL_CACHEINHIBIT \
358 | BATL_GUARDEDSTORAGE)
359 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
360 | BATU_BL_1M | BATU_VS | BATU_VP)
361 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
362 | BATL_PP_RW | BATL_CACHEINHIBIT)
363 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
367 * BAT4 32M Cache-inhibited, guarded
368 * 0xe200_0000 1M PCI-Express 2 I/O
369 * 0xe300_0000 1M PCI-Express 1 I/O
372 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
373 | BATL_GUARDEDSTORAGE)
374 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
375 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
376 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
379 * BAT5 128K Cacheable, non-guarded
380 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
382 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
383 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
384 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
385 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
388 * BAT6 256M Cache-inhibited, guarded
389 * 0xf000_0000 256M FLASH
391 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
392 | BATL_GUARDEDSTORAGE)
393 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
394 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
395 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
397 /* Map the last 1M of flash where we're running from reset */
398 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
399 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
400 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
401 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
403 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
406 * BAT7 4M Cache-inhibited, guarded
407 * 0xe800_0000 4M PIXIS
409 #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
410 | BATL_GUARDEDSTORAGE)
411 #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
412 #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
413 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
418 #ifndef CONFIG_SYS_RAMBOOT
419 #define CONFIG_ENV_IS_IN_FLASH 1
420 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
421 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */
422 #define CONFIG_ENV_SIZE 0x2000
424 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
425 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
426 #define CONFIG_ENV_SIZE 0x2000
429 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
430 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
435 #define CONFIG_BOOTP_BOOTFILESIZE
436 #define CONFIG_BOOTP_BOOTPATH
437 #define CONFIG_BOOTP_GATEWAY
438 #define CONFIG_BOOTP_HOSTNAME
441 * Command line configuration.
444 #if defined(CONFIG_PCI)
445 #define CONFIG_CMD_PCI
449 #define CONFIG_WATCHDOG /* watchdog enabled */
450 #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
453 * Miscellaneous configurable options
455 #define CONFIG_SYS_LONGHELP /* undef to save memory */
456 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
457 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
459 #if defined(CONFIG_CMD_KGDB)
460 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
462 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
465 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
466 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
467 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
470 * For booting Linux, the board info and command line data
471 * have to be in the first 8 MB of memory, since this is
472 * the maximum mapped by the Linux kernel during initialization.
474 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
475 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */
477 #if defined(CONFIG_CMD_KGDB)
478 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
482 * Environment Configuration
484 #define CONFIG_IPADDR 192.168.1.100
486 #define CONFIG_HOSTNAME unknown
487 #define CONFIG_ROOTPATH "/opt/nfsroot"
488 #define CONFIG_BOOTFILE "uImage"
489 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin
491 #define CONFIG_SERVERIP 192.168.1.1
492 #define CONFIG_GATEWAYIP 192.168.1.1
493 #define CONFIG_NETMASK 255.255.255.0
495 /* default location for tftp and bootm */
496 #define CONFIG_LOADADDR 0x10000000
498 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
500 #define CONFIG_BAUDRATE 115200
502 #if defined(CONFIG_PCI1)
504 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
505 "echo e;md ${a}e00 9\0" \
506 "pci1regs=setenv a e0008; run pcireg\0" \
507 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
508 "pci d.w $b.0 56 1\0" \
509 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
510 "pci w.w $b.0 56 ffff\0" \
511 "pci1err=setenv a e0008; run pcierr\0" \
512 "pci1errc=setenv a e0008; run pcierrc\0"
517 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
519 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
520 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
521 "pcie1regs=setenv a e000a; run pciereg\0" \
522 "pcie2regs=setenv a e0009; run pciereg\0" \
523 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
524 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
525 "pci d $b.0 130 1\0" \
526 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
527 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
528 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
529 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
530 "pcie1err=setenv a e000a; run pcieerr\0" \
531 "pcie2err=setenv a e0009; run pcieerr\0" \
532 "pcie1errc=setenv a e000a; run pcieerrc\0" \
533 "pcie2errc=setenv a e0009; run pcieerrc\0"
539 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
540 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
541 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
542 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
543 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
544 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
545 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
546 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
549 #define CONFIG_EXTRA_ENV_SETTINGS \
551 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
552 "tftpflash=tftpboot $loadaddr $uboot; " \
553 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
555 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
557 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
559 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
561 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
563 "consoledev=ttyS0\0" \
564 "ramdiskaddr=0x18000000\0" \
565 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
566 "fdtaddr=0x17c00000\0" \
567 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
569 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
570 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
572 "eoi=mw e00400b0 0\0" \
573 "iack=md e00400a0 1\0" \
574 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
575 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
577 "ddr1regs=setenv a e0002; run ddrreg\0" \
578 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
579 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
580 "md ${a}e60 1; md ${a}ef0 1d\0" \
581 "guregs=setenv a e00e0; run gureg\0" \
582 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
583 "mcmregs=setenv a e0001; run mcmreg\0" \
584 "diuregs=md e002c000 1d\0" \
585 "dium=mw e002c01c\0" \
586 "diuerr=md e002c014 1\0" \
587 "pmregs=md e00e1000 2b\0" \
588 "lawregs=md e0000c08 4b\0" \
589 "lbcregs=md e0005000 36\0" \
590 "dma0regs=md e0021100 12\0" \
591 "dma1regs=md e0021180 12\0" \
592 "dma2regs=md e0021200 12\0" \
593 "dma3regs=md e0021280 12\0" \
598 #define CONFIG_EXTRA_ENV_SETTINGS \
600 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
601 "consoledev=ttyS0\0" \
602 "ramdiskaddr=0x18000000\0" \
603 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
604 "fdtaddr=0x17c00000\0" \
605 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
609 #define CONFIG_NFSBOOTCOMMAND \
610 "setenv bootargs root=/dev/nfs rw " \
611 "nfsroot=$serverip:$rootpath " \
612 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
613 "console=$consoledev,$baudrate $othbootargs;" \
614 "tftp $loadaddr $bootfile;" \
615 "tftp $fdtaddr $fdtfile;" \
616 "bootm $loadaddr - $fdtaddr"
618 #define CONFIG_RAMBOOTCOMMAND \
619 "setenv bootargs root=/dev/ram rw " \
620 "console=$consoledev,$baudrate $othbootargs;" \
621 "tftp $ramdiskaddr $ramdiskfile;" \
622 "tftp $loadaddr $bootfile;" \
623 "tftp $fdtaddr $fdtfile;" \
624 "bootm $loadaddr $ramdiskaddr $fdtaddr"
626 #define CONFIG_BOOTCOMMAND \
627 "setenv bootargs root=/dev/$bdev rw " \
628 "console=$consoledev,$baudrate $othbootargs;" \
629 "tftp $loadaddr $bootfile;" \
630 "tftp $fdtaddr $fdtfile;" \
631 "bootm $loadaddr - $fdtaddr"
633 #endif /* __CONFIG_H */