2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
8 * MPC8610HPCD board configuration file
14 /* High Level Configuration Options */
15 #define CONFIG_MPC8610 1 /* MPC8610 specific */
16 #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */
17 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
19 #define CONFIG_SYS_TEXT_BASE 0xfff00000
22 #define CONFIG_FSL_DIU_FB
24 #ifdef CONFIG_FSL_DIU_FB
25 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
27 #define CONFIG_CMD_BMP
28 #define CONFIG_CFB_CONSOLE
29 #define CONFIG_VIDEO_SW_CURSOR
30 #define CONFIG_VGA_AS_SINGLE_DEVICE
31 #define CONFIG_VIDEO_LOGO
32 #define CONFIG_VIDEO_BMP_LOGO
36 #define CONFIG_SYS_DIAG_ADDR 0xff800000
40 * virtual address to be used for temporary mappings. There
41 * should be 128k free at this VA.
43 #define CONFIG_SYS_SCRATCH_VA 0xc0000000
45 #define CONFIG_PCI 1 /* Enable PCI/PCIE*/
46 #define CONFIG_PCI1 1 /* PCI controller 1 */
47 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
48 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
49 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
50 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
51 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
52 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
54 #define CONFIG_ENV_OVERWRITE
55 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
57 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
58 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */
59 #define CONFIG_ALTIVEC 1
62 * L2CR setup -- make sure this is right for your board!
66 #define L2_ENABLE (L2CR_L2E |0x00100000 )
68 #ifndef CONFIG_SYS_CLK_FREQ
69 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
72 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
73 #define CONFIG_MISC_INIT_R 1
75 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
76 #define CONFIG_SYS_MEMTEST_END 0x00400000
79 * Base addresses -- Note these are effective addresses where the
80 * actual resources get mapped (not physical addresses)
82 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
83 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
84 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
86 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
87 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
88 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
91 #define CONFIG_SYS_FSL_DDR2
92 #undef CONFIG_FSL_DDR_INTERACTIVE
93 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */
94 #define CONFIG_DDR_SPD
96 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
97 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
99 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
100 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
101 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
102 #define CONFIG_VERY_BIG_RAM
104 #define CONFIG_NUM_DDR_CONTROLLERS 1
105 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
106 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
108 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
110 /* These are used when DDR doesn't use SPD. */
111 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
114 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
115 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
116 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
117 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
118 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
119 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
120 #define CONFIG_SYS_DDR_MODE_1 0x00480432
121 #define CONFIG_SYS_DDR_MODE_2 0x00000000
122 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
123 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
124 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
125 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
126 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
127 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
128 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
130 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
131 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
132 #define CONFIG_SYS_DDR_SBE 0x000f0000
136 #define CONFIG_ID_EEPROM
137 #define CONFIG_SYS_I2C_EEPROM_NXID
138 #define CONFIG_ID_EEPROM
139 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
140 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
142 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
143 #define CONFIG_SYS_FLASH_BASE2 0xf8000000
145 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
147 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */
148 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/
150 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */
151 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */
153 #define CONFIG_SYS_BR2_PRELIM 0xf0000000
154 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */
156 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */
157 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
159 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
160 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */
161 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
162 #define PIXIS_VER 0x1 /* Board version at offset 1 */
163 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
164 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
165 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */
166 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
167 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/
168 #define PIXIS_VCTL 0x10 /* VELA Control Register */
169 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
170 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
171 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
172 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
173 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
174 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
175 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
176 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */
178 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
179 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
181 #undef CONFIG_SYS_FLASH_CHECKSUM
182 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
183 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
184 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
185 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
187 #define CONFIG_FLASH_CFI_DRIVER
188 #define CONFIG_SYS_FLASH_CFI
189 #define CONFIG_SYS_FLASH_EMPTY_INFO
191 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
192 #define CONFIG_SYS_RAMBOOT
194 #undef CONFIG_SYS_RAMBOOT
197 #if defined(CONFIG_SYS_RAMBOOT)
198 #undef CONFIG_SPD_EEPROM
199 #define CONFIG_SYS_SDRAM_SIZE 256
202 #undef CONFIG_CLOCKS_IN_MHZ
204 #define CONFIG_SYS_INIT_RAM_LOCK 1
205 #ifndef CONFIG_SYS_INIT_RAM_LOCK
206 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
208 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */
210 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
212 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
213 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
215 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
216 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
219 #define CONFIG_CONS_INDEX 1
220 #define CONFIG_SYS_NS16550_SERIAL
221 #define CONFIG_SYS_NS16550_REG_SIZE 1
222 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
224 #define CONFIG_SYS_BAUDRATE_TABLE \
225 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
227 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
228 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
230 /* maximum size of the flat tree (8K) */
231 #define OF_FLAT_TREE_MAX_SIZE 8192
236 #define CONFIG_SYS_I2C
237 #define CONFIG_SYS_I2C_FSL
238 #define CONFIG_SYS_FSL_I2C_SPEED 400000
239 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
240 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
241 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
245 * Addresses are mapped 1-1.
247 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
248 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
249 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
250 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
251 #define CONFIG_SYS_PCI1_IO_BUS 0x0000000
252 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
253 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
254 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
256 /* controller 1, Base address 0xa000 */
257 #define CONFIG_SYS_PCIE1_NAME "ULI"
258 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
259 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
260 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
261 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
262 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
263 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
265 /* controller 2, Base Address 0x9000 */
266 #define CONFIG_SYS_PCIE2_NAME "Slot 1"
267 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
268 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
269 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
270 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */
271 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
272 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */
274 #if defined(CONFIG_PCI)
276 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
278 #define CONFIG_PCI_PNP /* do pci plug-and-play */
279 #define CONFIG_CMD_REGINFO
281 #define CONFIG_ULI526X
282 #ifdef CONFIG_ULI526X
285 /************************************************************
287 ************************************************************/
288 #define CONFIG_PCI_OHCI 1
289 #define CONFIG_USB_OHCI_NEW 1
290 #define CONFIG_USB_KEYBOARD 1
291 #define CONFIG_SYS_STDIO_DEREGISTER
292 #define CONFIG_SYS_USB_EVENT_POLL 1
293 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
294 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
295 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
297 #if !defined(CONFIG_PCI_PNP)
298 #define PCI_ENET0_IOADDR 0xe0000000
299 #define PCI_ENET0_MEMADDR 0xe0000000
300 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
303 #define CONFIG_DOS_PARTITION
304 #define CONFIG_SCSI_AHCI
306 #ifdef CONFIG_SCSI_AHCI
307 #define CONFIG_LIBATA
308 #define CONFIG_SATA_ULI5288
309 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
310 #define CONFIG_SYS_SCSI_MAX_LUN 1
311 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
312 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
315 #endif /* CONFIG_PCI */
318 * BAT0 2G Cacheable, non-guarded
321 #define CONFIG_SYS_DBAT0L (BATL_PP_RW)
322 #define CONFIG_SYS_IBAT0L (BATL_PP_RW)
325 * BAT1 1G Cache-inhibited, guarded
326 * 0x8000_0000 256M PCI-1 Memory
327 * 0xa000_0000 256M PCI-Express 1 Memory
328 * 0x9000_0000 256M PCI-Express 2 Memory
331 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
332 | BATL_GUARDEDSTORAGE)
333 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
334 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
335 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
338 * BAT2 16M Cache-inhibited, guarded
339 * 0xe100_0000 1M PCI-1 I/O
342 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
343 | BATL_GUARDEDSTORAGE)
344 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
345 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
346 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
349 * BAT3 4M Cache-inhibited, guarded
350 * 0xe000_0000 4M CCSR
353 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
354 | BATL_GUARDEDSTORAGE)
355 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
356 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
357 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
359 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
360 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
361 | BATL_PP_RW | BATL_CACHEINHIBIT \
362 | BATL_GUARDEDSTORAGE)
363 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
364 | BATU_BL_1M | BATU_VS | BATU_VP)
365 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
366 | BATL_PP_RW | BATL_CACHEINHIBIT)
367 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
371 * BAT4 32M Cache-inhibited, guarded
372 * 0xe200_0000 1M PCI-Express 2 I/O
373 * 0xe300_0000 1M PCI-Express 1 I/O
376 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
377 | BATL_GUARDEDSTORAGE)
378 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
379 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
380 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
383 * BAT5 128K Cacheable, non-guarded
384 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
386 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
387 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
388 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
389 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
392 * BAT6 256M Cache-inhibited, guarded
393 * 0xf000_0000 256M FLASH
395 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
396 | BATL_GUARDEDSTORAGE)
397 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
398 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
399 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
401 /* Map the last 1M of flash where we're running from reset */
402 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
403 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
404 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
405 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
407 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
410 * BAT7 4M Cache-inhibited, guarded
411 * 0xe800_0000 4M PIXIS
413 #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
414 | BATL_GUARDEDSTORAGE)
415 #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
416 #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
417 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
422 #ifndef CONFIG_SYS_RAMBOOT
423 #define CONFIG_ENV_IS_IN_FLASH 1
424 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
425 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */
426 #define CONFIG_ENV_SIZE 0x2000
428 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
429 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
430 #define CONFIG_ENV_SIZE 0x2000
433 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
434 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
439 #define CONFIG_BOOTP_BOOTFILESIZE
440 #define CONFIG_BOOTP_BOOTPATH
441 #define CONFIG_BOOTP_GATEWAY
442 #define CONFIG_BOOTP_HOSTNAME
445 * Command line configuration.
448 #if defined(CONFIG_PCI)
449 #define CONFIG_CMD_PCI
453 #define CONFIG_WATCHDOG /* watchdog enabled */
454 #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
457 * Miscellaneous configurable options
459 #define CONFIG_SYS_LONGHELP /* undef to save memory */
460 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
461 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
463 #if defined(CONFIG_CMD_KGDB)
464 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
466 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
469 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
470 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
471 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
474 * For booting Linux, the board info and command line data
475 * have to be in the first 8 MB of memory, since this is
476 * the maximum mapped by the Linux kernel during initialization.
478 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
479 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */
481 #if defined(CONFIG_CMD_KGDB)
482 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
486 * Environment Configuration
488 #define CONFIG_IPADDR 192.168.1.100
490 #define CONFIG_HOSTNAME unknown
491 #define CONFIG_ROOTPATH "/opt/nfsroot"
492 #define CONFIG_BOOTFILE "uImage"
493 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin
495 #define CONFIG_SERVERIP 192.168.1.1
496 #define CONFIG_GATEWAYIP 192.168.1.1
497 #define CONFIG_NETMASK 255.255.255.0
499 /* default location for tftp and bootm */
500 #define CONFIG_LOADADDR 0x10000000
502 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
504 #define CONFIG_BAUDRATE 115200
506 #if defined(CONFIG_PCI1)
508 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
509 "echo e;md ${a}e00 9\0" \
510 "pci1regs=setenv a e0008; run pcireg\0" \
511 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
512 "pci d.w $b.0 56 1\0" \
513 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
514 "pci w.w $b.0 56 ffff\0" \
515 "pci1err=setenv a e0008; run pcierr\0" \
516 "pci1errc=setenv a e0008; run pcierrc\0"
521 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
523 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
524 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
525 "pcie1regs=setenv a e000a; run pciereg\0" \
526 "pcie2regs=setenv a e0009; run pciereg\0" \
527 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
528 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
529 "pci d $b.0 130 1\0" \
530 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
531 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
532 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
533 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
534 "pcie1err=setenv a e000a; run pcieerr\0" \
535 "pcie2err=setenv a e0009; run pcieerr\0" \
536 "pcie1errc=setenv a e000a; run pcieerrc\0" \
537 "pcie2errc=setenv a e0009; run pcieerrc\0"
543 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
544 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
545 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
546 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
547 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
548 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
549 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
550 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
553 #define CONFIG_EXTRA_ENV_SETTINGS \
555 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
556 "tftpflash=tftpboot $loadaddr $uboot; " \
557 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
559 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
561 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
563 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
565 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
567 "consoledev=ttyS0\0" \
568 "ramdiskaddr=0x18000000\0" \
569 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
570 "fdtaddr=0x17c00000\0" \
571 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
573 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
574 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
576 "eoi=mw e00400b0 0\0" \
577 "iack=md e00400a0 1\0" \
578 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
579 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
581 "ddr1regs=setenv a e0002; run ddrreg\0" \
582 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
583 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
584 "md ${a}e60 1; md ${a}ef0 1d\0" \
585 "guregs=setenv a e00e0; run gureg\0" \
586 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
587 "mcmregs=setenv a e0001; run mcmreg\0" \
588 "diuregs=md e002c000 1d\0" \
589 "dium=mw e002c01c\0" \
590 "diuerr=md e002c014 1\0" \
591 "pmregs=md e00e1000 2b\0" \
592 "lawregs=md e0000c08 4b\0" \
593 "lbcregs=md e0005000 36\0" \
594 "dma0regs=md e0021100 12\0" \
595 "dma1regs=md e0021180 12\0" \
596 "dma2regs=md e0021200 12\0" \
597 "dma3regs=md e0021280 12\0" \
602 #define CONFIG_EXTRA_ENV_SETTINGS \
604 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
605 "consoledev=ttyS0\0" \
606 "ramdiskaddr=0x18000000\0" \
607 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
608 "fdtaddr=0x17c00000\0" \
609 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
613 #define CONFIG_NFSBOOTCOMMAND \
614 "setenv bootargs root=/dev/nfs rw " \
615 "nfsroot=$serverip:$rootpath " \
616 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
617 "console=$consoledev,$baudrate $othbootargs;" \
618 "tftp $loadaddr $bootfile;" \
619 "tftp $fdtaddr $fdtfile;" \
620 "bootm $loadaddr - $fdtaddr"
622 #define CONFIG_RAMBOOTCOMMAND \
623 "setenv bootargs root=/dev/ram rw " \
624 "console=$consoledev,$baudrate $othbootargs;" \
625 "tftp $ramdiskaddr $ramdiskfile;" \
626 "tftp $loadaddr $bootfile;" \
627 "tftp $fdtaddr $fdtfile;" \
628 "bootm $loadaddr $ramdiskaddr $fdtaddr"
630 #define CONFIG_BOOTCOMMAND \
631 "setenv bootargs root=/dev/$bdev rw " \
632 "console=$consoledev,$baudrate $othbootargs;" \
633 "tftp $loadaddr $bootfile;" \
634 "tftp $fdtaddr $fdtfile;" \
635 "bootm $loadaddr - $fdtaddr"
637 #endif /* __CONFIG_H */