2 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * mpc8572ds board configuration file
14 #include "../board/freescale/common/ics307_clk.h"
16 #ifndef CONFIG_SYS_TEXT_BASE
17 #define CONFIG_SYS_TEXT_BASE 0xeff40000
20 #ifndef CONFIG_RESET_VECTOR_ADDRESS
21 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
24 #ifndef CONFIG_SYS_MONITOR_BASE
25 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
28 /* High Level Configuration Options */
29 #define CONFIG_MP 1 /* support multiple processors */
31 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
32 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
33 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
34 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
35 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
36 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
37 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
38 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
40 #define CONFIG_TSEC_ENET /* tsec ethernet support */
41 #define CONFIG_ENV_OVERWRITE
43 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
44 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
45 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
48 * These can be toggled for performance analysis, otherwise use default.
50 #define CONFIG_L2_CACHE /* toggle L2 cache */
51 #define CONFIG_BTB /* toggle branch predition */
53 #define CONFIG_ENABLE_36BIT_PHYS 1
55 #ifdef CONFIG_PHYS_64BIT
56 #define CONFIG_ADDR_MAP 1
57 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
60 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
61 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
62 #define CONFIG_PANIC_HANG /* do not reset board on panic */
65 * Config the L2 Cache as L2 SRAM
67 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
68 #ifdef CONFIG_PHYS_64BIT
69 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
71 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
73 #define CONFIG_SYS_L2_SIZE (512 << 10)
74 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
76 #define CONFIG_SYS_CCSRBAR 0xffe00000
77 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
79 #if defined(CONFIG_NAND_SPL)
80 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
84 #define CONFIG_VERY_BIG_RAM
85 #define CONFIG_SYS_FSL_DDR2
86 #undef CONFIG_FSL_DDR_INTERACTIVE
87 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
88 #define CONFIG_DDR_SPD
90 #define CONFIG_DDR_ECC
91 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
92 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
94 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
95 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
97 #define CONFIG_NUM_DDR_CONTROLLERS 2
98 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
99 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
101 /* I2C addresses of SPD EEPROMs */
102 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
103 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
104 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
106 /* These are used when DDR doesn't use SPD. */
107 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
108 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
109 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
110 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
111 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
112 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634
113 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf
114 #define CONFIG_SYS_DDR_MODE_1 0x00440462
115 #define CONFIG_SYS_DDR_MODE_2 0x00000000
116 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100
117 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
118 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
119 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
120 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
121 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
122 #define CONFIG_SYS_DDR_CONTROL2 0x24400000
124 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
125 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
126 #define CONFIG_SYS_DDR_SBE 0x00010000
129 * Make sure required options are set
131 #ifndef CONFIG_SPD_EEPROM
132 #error ("CONFIG_SPD_EEPROM is required")
135 #undef CONFIG_CLOCKS_IN_MHZ
140 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
141 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
142 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
143 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
145 * Localbus cacheable (TBD)
146 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
148 * Localbus non-cacheable
149 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
150 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
151 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
152 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
153 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
154 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
158 * Local Bus Definitions
160 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
161 #ifdef CONFIG_PHYS_64BIT
162 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
164 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
167 #define CONFIG_FLASH_BR_PRELIM \
168 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
169 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
171 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
172 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
174 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
175 #define CONFIG_SYS_FLASH_QUIET_TEST
176 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
178 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
179 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
180 #undef CONFIG_SYS_FLASH_CHECKSUM
181 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
182 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
184 #undef CONFIG_SYS_RAMBOOT
186 #define CONFIG_FLASH_CFI_DRIVER
187 #define CONFIG_SYS_FLASH_CFI
188 #define CONFIG_SYS_FLASH_EMPTY_INFO
189 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
191 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
193 #define CONFIG_HWCONFIG /* enable hwconfig */
194 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
195 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
196 #ifdef CONFIG_PHYS_64BIT
197 #define PIXIS_BASE_PHYS 0xfffdf0000ull
199 #define PIXIS_BASE_PHYS PIXIS_BASE
202 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
203 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
205 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
206 #define PIXIS_VER 0x1 /* Board version at offset 1 */
207 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
208 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
209 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
210 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
211 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
212 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
213 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
214 #define PIXIS_VCTL 0x10 /* VELA Control Register */
215 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
216 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
217 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
218 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
219 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
220 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
221 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
222 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
223 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
224 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
225 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
226 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
227 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
228 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
229 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
230 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
231 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
232 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
233 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
234 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
235 #define PIXIS_LED 0x25 /* LED Register */
237 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
239 /* old pixis referenced names */
240 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
241 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
242 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
243 #define PIXIS_VSPEED2_TSEC1SER 0x8
244 #define PIXIS_VSPEED2_TSEC2SER 0x4
245 #define PIXIS_VSPEED2_TSEC3SER 0x2
246 #define PIXIS_VSPEED2_TSEC4SER 0x1
247 #define PIXIS_VCFGEN1_TSEC1SER 0x20
248 #define PIXIS_VCFGEN1_TSEC2SER 0x20
249 #define PIXIS_VCFGEN1_TSEC3SER 0x20
250 #define PIXIS_VCFGEN1_TSEC4SER 0x20
251 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
252 | PIXIS_VSPEED2_TSEC2SER \
253 | PIXIS_VSPEED2_TSEC3SER \
254 | PIXIS_VSPEED2_TSEC4SER)
255 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
256 | PIXIS_VCFGEN1_TSEC2SER \
257 | PIXIS_VCFGEN1_TSEC3SER \
258 | PIXIS_VCFGEN1_TSEC4SER)
260 #define CONFIG_SYS_INIT_RAM_LOCK 1
261 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
262 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
264 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
265 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
267 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
268 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
270 #ifndef CONFIG_NAND_SPL
271 #define CONFIG_SYS_NAND_BASE 0xffa00000
272 #ifdef CONFIG_PHYS_64BIT
273 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
275 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
278 #define CONFIG_SYS_NAND_BASE 0xfff00000
279 #ifdef CONFIG_PHYS_64BIT
280 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
282 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
286 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
287 CONFIG_SYS_NAND_BASE + 0x40000, \
288 CONFIG_SYS_NAND_BASE + 0x80000,\
289 CONFIG_SYS_NAND_BASE + 0xC0000}
290 #define CONFIG_SYS_MAX_NAND_DEVICE 4
291 #define CONFIG_CMD_NAND 1
292 #define CONFIG_NAND_FSL_ELBC 1
293 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
294 #define CONFIG_SYS_NAND_MAX_OOBFREE 5
295 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
297 /* NAND boot: 4K NAND loader config */
298 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
299 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
300 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
301 #define CONFIG_SYS_NAND_U_BOOT_START \
302 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
303 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
304 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
305 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
307 /* NAND flash config */
308 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
309 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
310 | BR_PS_8 /* Port Size = 8 bit */ \
311 | BR_MS_FCM /* MSEL = FCM */ \
313 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
314 | OR_FCM_PGS /* Large Page*/ \
322 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
323 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
324 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
325 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
326 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
327 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
328 | BR_PS_8 /* Port Size = 8 bit */ \
329 | BR_MS_FCM /* MSEL = FCM */ \
331 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
332 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
333 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
334 | BR_PS_8 /* Port Size = 8 bit */ \
335 | BR_MS_FCM /* MSEL = FCM */ \
337 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
339 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
340 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
341 | BR_PS_8 /* Port Size = 8 bit */ \
342 | BR_MS_FCM /* MSEL = FCM */ \
344 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
346 /* Serial Port - controlled on board with jumper J8
350 #define CONFIG_CONS_INDEX 1
351 #define CONFIG_SYS_NS16550_SERIAL
352 #define CONFIG_SYS_NS16550_REG_SIZE 1
353 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
354 #ifdef CONFIG_NAND_SPL
355 #define CONFIG_NS16550_MIN_FUNCTIONS
358 #define CONFIG_SYS_BAUDRATE_TABLE \
359 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
361 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
362 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
365 #define CONFIG_SYS_I2C
366 #define CONFIG_SYS_I2C_FSL
367 #define CONFIG_SYS_FSL_I2C_SPEED 400000
368 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
369 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
370 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
371 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
372 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
373 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
374 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
379 #define CONFIG_ID_EEPROM
380 #ifdef CONFIG_ID_EEPROM
381 #define CONFIG_SYS_I2C_EEPROM_NXID
383 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
384 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
385 #define CONFIG_SYS_EEPROM_BUS_NUM 1
389 * Memory space is mapped 1-1, but I/O space must start from 0.
392 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
393 #define CONFIG_SYS_PCIE3_NAME "ULI"
394 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
395 #ifdef CONFIG_PHYS_64BIT
396 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
397 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
399 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
400 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
402 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
403 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
404 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
405 #ifdef CONFIG_PHYS_64BIT
406 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
408 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
410 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
412 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
413 #define CONFIG_SYS_PCIE2_NAME "Slot 1"
414 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
415 #ifdef CONFIG_PHYS_64BIT
416 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
417 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
419 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
420 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
422 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
423 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
424 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
425 #ifdef CONFIG_PHYS_64BIT
426 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
428 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
430 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
432 /* controller 1, Slot 1, tgtid 1, Base address a000 */
433 #define CONFIG_SYS_PCIE1_NAME "Slot 2"
434 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
435 #ifdef CONFIG_PHYS_64BIT
436 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
437 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
439 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
440 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
442 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
443 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
444 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
445 #ifdef CONFIG_PHYS_64BIT
446 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
448 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
450 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
452 #if defined(CONFIG_PCI)
454 /*PCIE video card used*/
455 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
459 #if defined(CONFIG_VIDEO)
460 #define CONFIG_BIOSEMU
461 #define CONFIG_ATI_RADEON_FB
462 #define CONFIG_VIDEO_LOGO
463 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
466 #undef CONFIG_EEPRO100
469 #ifndef CONFIG_PCI_PNP
470 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
471 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
472 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
475 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
476 #define CONFIG_DOS_PARTITION
477 #define CONFIG_SCSI_AHCI
479 #ifdef CONFIG_SCSI_AHCI
480 #define CONFIG_LIBATA
481 #define CONFIG_SATA_ULI5288
482 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
483 #define CONFIG_SYS_SCSI_MAX_LUN 1
484 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
485 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
488 #endif /* CONFIG_PCI */
490 #if defined(CONFIG_TSEC_ENET)
492 #define CONFIG_MII 1 /* MII PHY management */
493 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
494 #define CONFIG_TSEC1 1
495 #define CONFIG_TSEC1_NAME "eTSEC1"
496 #define CONFIG_TSEC2 1
497 #define CONFIG_TSEC2_NAME "eTSEC2"
498 #define CONFIG_TSEC3 1
499 #define CONFIG_TSEC3_NAME "eTSEC3"
500 #define CONFIG_TSEC4 1
501 #define CONFIG_TSEC4_NAME "eTSEC4"
503 #define CONFIG_PIXIS_SGMII_CMD
504 #define CONFIG_FSL_SGMII_RISER 1
505 #define SGMII_RISER_PHY_OFFSET 0x1c
507 #ifdef CONFIG_FSL_SGMII_RISER
508 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
511 #define TSEC1_PHY_ADDR 0
512 #define TSEC2_PHY_ADDR 1
513 #define TSEC3_PHY_ADDR 2
514 #define TSEC4_PHY_ADDR 3
516 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
517 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
518 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
519 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
521 #define TSEC1_PHYIDX 0
522 #define TSEC2_PHYIDX 0
523 #define TSEC3_PHYIDX 0
524 #define TSEC4_PHYIDX 0
526 #define CONFIG_ETHPRIME "eTSEC1"
528 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
529 #endif /* CONFIG_TSEC_ENET */
535 #if defined(CONFIG_SYS_RAMBOOT)
538 #define CONFIG_ENV_IS_IN_FLASH 1
539 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
540 #define CONFIG_ENV_ADDR 0xfff80000
542 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
544 #define CONFIG_ENV_SIZE 0x2000
545 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
548 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
549 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
552 * Command line configuration.
554 #define CONFIG_CMD_ERRATA
555 #define CONFIG_CMD_IRQ
556 #define CONFIG_CMD_REGINFO
558 #if defined(CONFIG_PCI)
559 #define CONFIG_CMD_PCI
566 #define CONFIG_USB_EHCI
568 #ifdef CONFIG_USB_EHCI
569 #define CONFIG_USB_EHCI_PCI
570 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
571 #define CONFIG_PCI_EHCI_DEVICE 0
572 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
575 #undef CONFIG_WATCHDOG /* watchdog disabled */
578 * Miscellaneous configurable options
580 #define CONFIG_SYS_LONGHELP /* undef to save memory */
581 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
582 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
583 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
584 #if defined(CONFIG_CMD_KGDB)
585 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
587 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
589 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
590 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
591 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
594 * For booting Linux, the board info and command line data
595 * have to be in the first 64 MB of memory, since this is
596 * the maximum mapped by the Linux kernel during initialization.
598 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
599 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
601 #if defined(CONFIG_CMD_KGDB)
602 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
606 * Environment Configuration
608 #if defined(CONFIG_TSEC_ENET)
609 #define CONFIG_HAS_ETH0
610 #define CONFIG_HAS_ETH1
611 #define CONFIG_HAS_ETH2
612 #define CONFIG_HAS_ETH3
615 #define CONFIG_IPADDR 192.168.1.254
617 #define CONFIG_HOSTNAME unknown
618 #define CONFIG_ROOTPATH "/opt/nfsroot"
619 #define CONFIG_BOOTFILE "uImage"
620 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
622 #define CONFIG_SERVERIP 192.168.1.1
623 #define CONFIG_GATEWAYIP 192.168.1.1
624 #define CONFIG_NETMASK 255.255.255.0
626 /* default location for tftp and bootm */
627 #define CONFIG_LOADADDR 1000000
629 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
631 #define CONFIG_BAUDRATE 115200
633 #define CONFIG_EXTRA_ENV_SETTINGS \
634 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
636 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
637 "tftpflash=tftpboot $loadaddr $uboot; " \
638 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
640 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
642 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
644 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
646 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
648 "consoledev=ttyS0\0" \
649 "ramdiskaddr=2000000\0" \
650 "ramdiskfile=8572ds/ramdisk.uboot\0" \
651 "fdtaddr=1e00000\0" \
652 "fdtfile=8572ds/mpc8572ds.dtb\0" \
655 #define CONFIG_HDBOOT \
656 "setenv bootargs root=/dev/$bdev rw " \
657 "console=$consoledev,$baudrate $othbootargs;" \
658 "tftp $loadaddr $bootfile;" \
659 "tftp $fdtaddr $fdtfile;" \
660 "bootm $loadaddr - $fdtaddr"
662 #define CONFIG_NFSBOOTCOMMAND \
663 "setenv bootargs root=/dev/nfs rw " \
664 "nfsroot=$serverip:$rootpath " \
665 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
666 "console=$consoledev,$baudrate $othbootargs;" \
667 "tftp $loadaddr $bootfile;" \
668 "tftp $fdtaddr $fdtfile;" \
669 "bootm $loadaddr - $fdtaddr"
671 #define CONFIG_RAMBOOTCOMMAND \
672 "setenv bootargs root=/dev/ram rw " \
673 "console=$consoledev,$baudrate $othbootargs;" \
674 "tftp $ramdiskaddr $ramdiskfile;" \
675 "tftp $loadaddr $bootfile;" \
676 "tftp $fdtaddr $fdtfile;" \
677 "bootm $loadaddr $ramdiskaddr $fdtaddr"
679 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
681 #endif /* __CONFIG_H */