2 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * mpc8572ds board configuration file
30 /* High Level Configuration Options */
31 #define CONFIG_BOOKE 1 /* BOOKE */
32 #define CONFIG_E500 1 /* BOOKE e500 family */
33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
34 #define CONFIG_MPC8572 1
35 #define CONFIG_MPC8572DS 1
36 #define CONFIG_MP 1 /* support multiple processors */
37 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
39 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
40 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
41 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
42 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
43 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
44 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
45 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
47 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
49 #define CONFIG_TSEC_ENET /* tsec ethernet support */
50 #define CONFIG_ENV_OVERWRITE
53 * When initializing flash, if we cannot find the manufacturer ID,
54 * assume this is the AMD flash associated with the CDS board.
55 * This allows booting from a promjet.
57 #define CONFIG_ASSUME_AMD_FLASH
60 extern unsigned long get_board_sys_clk(unsigned long dummy);
61 extern unsigned long get_board_ddr_clk(unsigned long dummy);
63 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
64 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
65 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
66 #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
67 from ICS307 instead of switches */
70 * These can be toggled for performance analysis, otherwise use default.
72 #define CONFIG_L2_CACHE /* toggle L2 cache */
73 #define CONFIG_BTB /* toggle branch predition */
75 #define CONFIG_ENABLE_36BIT_PHYS 1
77 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
78 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
79 #define CONFIG_PANIC_HANG /* do not reset board on panic */
82 * Base addresses -- Note these are effective addresses where the
83 * actual resources get mapped (not physical addresses)
85 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
86 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
87 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
88 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
90 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
91 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
92 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
95 #define CONFIG_SYS_DDR_TLB_START 9
96 #define CONFIG_FSL_DDR2
97 #undef CONFIG_FSL_DDR_INTERACTIVE
98 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
99 #define CONFIG_DDR_SPD
100 #undef CONFIG_DDR_DLL
102 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
103 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
105 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
106 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
108 #define CONFIG_NUM_DDR_CONTROLLERS 2
109 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
110 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
112 /* I2C addresses of SPD EEPROMs */
113 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
114 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
115 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
117 /* These are used when DDR doesn't use SPD. */
118 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
119 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
120 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
121 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
122 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
123 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634
124 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf
125 #define CONFIG_SYS_DDR_MODE_1 0x00440462
126 #define CONFIG_SYS_DDR_MODE_2 0x00000000
127 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100
128 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
129 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
130 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
131 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
132 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
133 #define CONFIG_SYS_DDR_CONTROL2 0x24400000
135 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
136 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
137 #define CONFIG_SYS_DDR_SBE 0x00010000
140 * Make sure required options are set
142 #ifndef CONFIG_SPD_EEPROM
143 #error ("CONFIG_SPD_EEPROM is required")
146 #undef CONFIG_CLOCKS_IN_MHZ
151 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
152 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
153 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
154 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
156 * Localbus cacheable (TBD)
157 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
159 * Localbus non-cacheable
160 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
161 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
162 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
163 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
164 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
165 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
169 * Local Bus Definitions
171 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
172 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
174 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
175 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
177 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
178 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
180 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
181 #define CONFIG_SYS_FLASH_QUIET_TEST
182 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
184 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
185 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
186 #undef CONFIG_SYS_FLASH_CHECKSUM
187 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
188 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
190 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
192 #define CONFIG_FLASH_CFI_DRIVER
193 #define CONFIG_SYS_FLASH_CFI
194 #define CONFIG_SYS_FLASH_EMPTY_INFO
195 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
197 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
199 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
200 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
201 #define PIXIS_BASE_PHYS PIXIS_BASE
203 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
204 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
206 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
207 #define PIXIS_VER 0x1 /* Board version at offset 1 */
208 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
209 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
210 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
211 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
212 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
213 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
214 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
215 #define PIXIS_VCTL 0x10 /* VELA Control Register */
216 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
217 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
218 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
219 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
220 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
221 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
222 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
223 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
224 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
225 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
226 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
227 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
228 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
229 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
230 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
231 #define PIXIS_LED 0x25 /* LED Register */
233 /* old pixis referenced names */
234 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
235 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
236 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
237 #define PIXIS_VSPEED2_TSEC1SER 0x8
238 #define PIXIS_VSPEED2_TSEC2SER 0x4
239 #define PIXIS_VSPEED2_TSEC3SER 0x2
240 #define PIXIS_VSPEED2_TSEC4SER 0x1
241 #define PIXIS_VCFGEN1_TSEC1SER 0x20
242 #define PIXIS_VCFGEN1_TSEC2SER 0x20
243 #define PIXIS_VCFGEN1_TSEC3SER 0x20
244 #define PIXIS_VCFGEN1_TSEC4SER 0x20
245 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
246 | PIXIS_VSPEED2_TSEC2SER \
247 | PIXIS_VSPEED2_TSEC3SER \
248 | PIXIS_VSPEED2_TSEC4SER)
249 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
250 | PIXIS_VCFGEN1_TSEC2SER \
251 | PIXIS_VCFGEN1_TSEC3SER \
252 | PIXIS_VCFGEN1_TSEC4SER)
254 #define CONFIG_SYS_INIT_RAM_LOCK 1
255 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
256 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
258 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
259 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
260 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
262 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
263 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
265 #define CONFIG_SYS_NAND_BASE 0xffa00000
266 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
267 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
268 CONFIG_SYS_NAND_BASE + 0x40000, \
269 CONFIG_SYS_NAND_BASE + 0x80000,\
270 CONFIG_SYS_NAND_BASE + 0xC0000}
271 #define CONFIG_SYS_MAX_NAND_DEVICE 4
272 #define CONFIG_MTD_NAND_VERIFY_WRITE
273 #define CONFIG_CMD_NAND 1
274 #define CONFIG_NAND_FSL_ELBC 1
275 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
277 /* NAND flash config */
278 #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
279 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
280 | BR_PS_8 /* Port Size = 8 bit */ \
281 | BR_MS_FCM /* MSEL = FCM */ \
283 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
284 | OR_FCM_PGS /* Large Page*/ \
292 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
293 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
295 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
296 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
297 | BR_PS_8 /* Port Size = 8 bit */ \
298 | BR_MS_FCM /* MSEL = FCM */ \
300 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
301 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
302 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
303 | BR_PS_8 /* Port Size = 8 bit */ \
304 | BR_MS_FCM /* MSEL = FCM */ \
306 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
308 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
309 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
310 | BR_PS_8 /* Port Size = 8 bit */ \
311 | BR_MS_FCM /* MSEL = FCM */ \
313 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
316 /* Serial Port - controlled on board with jumper J8
320 #define CONFIG_CONS_INDEX 1
321 #undef CONFIG_SERIAL_SOFTWARE_FIFO
322 #define CONFIG_SYS_NS16550
323 #define CONFIG_SYS_NS16550_SERIAL
324 #define CONFIG_SYS_NS16550_REG_SIZE 1
325 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
327 #define CONFIG_SYS_BAUDRATE_TABLE \
328 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
330 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
331 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
333 /* Use the HUSH parser */
334 #define CONFIG_SYS_HUSH_PARSER
335 #ifdef CONFIG_SYS_HUSH_PARSER
336 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
340 * Pass open firmware flat tree
342 #define CONFIG_OF_LIBFDT 1
343 #define CONFIG_OF_BOARD_SETUP 1
344 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
346 #define CONFIG_SYS_64BIT_VSPRINTF 1
347 #define CONFIG_SYS_64BIT_STRTOUL 1
349 /* new uImage format support */
351 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
354 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
355 #define CONFIG_HARD_I2C /* I2C with hardware support */
356 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
357 #define CONFIG_I2C_MULTI_BUS
358 #define CONFIG_I2C_CMD_TREE
359 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
360 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
361 #define CONFIG_SYS_I2C_SLAVE 0x7F
362 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
363 #define CONFIG_SYS_I2C_OFFSET 0x3000
364 #define CONFIG_SYS_I2C2_OFFSET 0x3100
369 #define CONFIG_ID_EEPROM
370 #ifdef CONFIG_ID_EEPROM
371 #define CONFIG_SYS_I2C_EEPROM_NXID
373 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
374 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
375 #define CONFIG_SYS_EEPROM_BUS_NUM 1
379 * Memory space is mapped 1-1, but I/O space must start from 0.
382 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
383 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
384 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
385 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
386 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
387 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
388 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
389 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
390 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
392 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
393 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
394 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
395 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
396 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
397 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
398 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
399 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
400 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
402 /* controller 1, Slot 1, tgtid 1, Base address a000 */
403 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
404 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
405 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
406 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
407 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
408 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
409 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
410 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
412 #if defined(CONFIG_PCI)
414 /*PCIE video card used*/
415 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
420 #if defined(CONFIG_VIDEO)
421 #define CONFIG_BIOSEMU
422 #define CONFIG_CFB_CONSOLE
423 #define CONFIG_VIDEO_SW_CURSOR
424 #define CONFIG_VGA_AS_SINGLE_DEVICE
425 #define CONFIG_ATI_RADEON_FB
426 #define CONFIG_VIDEO_LOGO
427 /*#define CONFIG_CONSOLE_CURSOR*/
428 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
431 #define CONFIG_NET_MULTI
432 #define CONFIG_PCI_PNP /* do pci plug-and-play */
434 #undef CONFIG_EEPRO100
436 #undef CONFIG_RTL8139
438 #ifdef CONFIG_RTL8139
439 /* This macro is used by RTL8139 but not defined in PPC architecture */
440 #define KSEG1ADDR(x) (x)
441 #define _IO_BASE 0x00000000
444 #ifndef CONFIG_PCI_PNP
445 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
446 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
447 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
450 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
451 #define CONFIG_DOS_PARTITION
452 #define CONFIG_SCSI_AHCI
454 #ifdef CONFIG_SCSI_AHCI
455 #define CONFIG_SATA_ULI5288
456 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
457 #define CONFIG_SYS_SCSI_MAX_LUN 1
458 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
459 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
462 #endif /* CONFIG_PCI */
465 #if defined(CONFIG_TSEC_ENET)
467 #ifndef CONFIG_NET_MULTI
468 #define CONFIG_NET_MULTI 1
471 #define CONFIG_MII 1 /* MII PHY management */
472 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
473 #define CONFIG_TSEC1 1
474 #define CONFIG_TSEC1_NAME "eTSEC1"
475 #define CONFIG_TSEC2 1
476 #define CONFIG_TSEC2_NAME "eTSEC2"
477 #define CONFIG_TSEC3 1
478 #define CONFIG_TSEC3_NAME "eTSEC3"
479 #define CONFIG_TSEC4 1
480 #define CONFIG_TSEC4_NAME "eTSEC4"
482 #define CONFIG_PIXIS_SGMII_CMD
483 #define CONFIG_FSL_SGMII_RISER 1
484 #define SGMII_RISER_PHY_OFFSET 0x1c
486 #ifdef CONFIG_FSL_SGMII_RISER
487 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
490 #define TSEC1_PHY_ADDR 0
491 #define TSEC2_PHY_ADDR 1
492 #define TSEC3_PHY_ADDR 2
493 #define TSEC4_PHY_ADDR 3
495 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
496 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
497 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
498 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
500 #define TSEC1_PHYIDX 0
501 #define TSEC2_PHYIDX 0
502 #define TSEC3_PHYIDX 0
503 #define TSEC4_PHYIDX 0
505 #define CONFIG_ETHPRIME "eTSEC1"
507 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
508 #endif /* CONFIG_TSEC_ENET */
513 #define CONFIG_ENV_IS_IN_FLASH 1
514 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
515 #define CONFIG_ENV_ADDR 0xfff80000
517 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
519 #define CONFIG_ENV_SIZE 0x2000
520 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
522 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
523 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
526 * Command line configuration.
528 #include <config_cmd_default.h>
530 #define CONFIG_CMD_IRQ
531 #define CONFIG_CMD_PING
532 #define CONFIG_CMD_I2C
533 #define CONFIG_CMD_MII
534 #define CONFIG_CMD_ELF
535 #define CONFIG_CMD_IRQ
536 #define CONFIG_CMD_SETEXPR
538 #if defined(CONFIG_PCI)
539 #define CONFIG_CMD_PCI
540 #define CONFIG_CMD_BEDBUG
541 #define CONFIG_CMD_NET
542 #define CONFIG_CMD_SCSI
543 #define CONFIG_CMD_EXT2
546 #undef CONFIG_WATCHDOG /* watchdog disabled */
549 * Miscellaneous configurable options
551 #define CONFIG_SYS_LONGHELP /* undef to save memory */
552 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
553 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
554 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
555 #if defined(CONFIG_CMD_KGDB)
556 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
558 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
560 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
561 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
562 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
563 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
566 * For booting Linux, the board info and command line data
567 * have to be in the first 8 MB of memory, since this is
568 * the maximum mapped by the Linux kernel during initialization.
570 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
573 * Internal Definitions
577 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
578 #define BOOTFLAG_WARM 0x02 /* Software reboot */
580 #if defined(CONFIG_CMD_KGDB)
581 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
582 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
586 * Environment Configuration
589 /* The mac addresses for all ethernet interface */
590 #if defined(CONFIG_TSEC_ENET)
591 #define CONFIG_HAS_ETH0
592 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
593 #define CONFIG_HAS_ETH1
594 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
595 #define CONFIG_HAS_ETH2
596 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
597 #define CONFIG_HAS_ETH3
598 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
601 #define CONFIG_IPADDR 192.168.1.254
603 #define CONFIG_HOSTNAME unknown
604 #define CONFIG_ROOTPATH /opt/nfsroot
605 #define CONFIG_BOOTFILE uImage
606 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
608 #define CONFIG_SERVERIP 192.168.1.1
609 #define CONFIG_GATEWAYIP 192.168.1.1
610 #define CONFIG_NETMASK 255.255.255.0
612 /* default location for tftp and bootm */
613 #define CONFIG_LOADADDR 1000000
615 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
616 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
618 #define CONFIG_BAUDRATE 115200
620 #define CONFIG_EXTRA_ENV_SETTINGS \
621 "memctl_intlv_ctl=2\0" \
623 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
624 "tftpflash=tftpboot $loadaddr $uboot; " \
625 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
626 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
627 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
628 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
629 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
630 "consoledev=ttyS0\0" \
631 "ramdiskaddr=2000000\0" \
632 "ramdiskfile=8572ds/ramdisk.uboot\0" \
634 "fdtfile=8572ds/mpc8572ds.dtb\0" \
637 #define CONFIG_HDBOOT \
638 "setenv bootargs root=/dev/$bdev rw " \
639 "console=$consoledev,$baudrate $othbootargs;" \
640 "tftp $loadaddr $bootfile;" \
641 "tftp $fdtaddr $fdtfile;" \
642 "bootm $loadaddr - $fdtaddr"
644 #define CONFIG_NFSBOOTCOMMAND \
645 "setenv bootargs root=/dev/nfs rw " \
646 "nfsroot=$serverip:$rootpath " \
647 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
648 "console=$consoledev,$baudrate $othbootargs;" \
649 "tftp $loadaddr $bootfile;" \
650 "tftp $fdtaddr $fdtfile;" \
651 "bootm $loadaddr - $fdtaddr"
653 #define CONFIG_RAMBOOTCOMMAND \
654 "setenv bootargs root=/dev/ram rw " \
655 "console=$consoledev,$baudrate $othbootargs;" \
656 "tftp $ramdiskaddr $ramdiskfile;" \
657 "tftp $loadaddr $bootfile;" \
658 "tftp $fdtaddr $fdtfile;" \
659 "bootm $loadaddr $ramdiskaddr $fdtaddr"
661 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
663 #endif /* __CONFIG_H */