1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
7 * mpc8572ds board configuration file
13 #include <linux/stringify.h>
15 #include "../board/freescale/common/ics307_clk.h"
17 #ifndef CONFIG_RESET_VECTOR_ADDRESS
18 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
21 #ifndef CONFIG_SYS_MONITOR_BASE
22 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
25 /* High Level Configuration Options */
27 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
28 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
29 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
30 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
31 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
32 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
34 #define CONFIG_ENV_OVERWRITE
36 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
37 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
38 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
41 * These can be toggled for performance analysis, otherwise use default.
43 #define CONFIG_L2_CACHE /* toggle L2 cache */
44 #define CONFIG_BTB /* toggle branch predition */
46 #define CONFIG_ENABLE_36BIT_PHYS 1
49 * Config the L2 Cache as L2 SRAM
51 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
52 #ifdef CONFIG_PHYS_64BIT
53 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
55 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
57 #define CONFIG_SYS_L2_SIZE (512 << 10)
58 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
60 #define CONFIG_SYS_CCSRBAR 0xffe00000
61 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
63 #if defined(CONFIG_NAND_SPL)
64 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
68 #define CONFIG_VERY_BIG_RAM
69 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
70 #define CONFIG_DDR_SPD
72 #define CONFIG_DDR_ECC
73 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
74 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
76 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
77 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
79 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
80 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
82 /* I2C addresses of SPD EEPROMs */
83 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
84 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
85 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
87 /* These are used when DDR doesn't use SPD. */
88 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
89 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
90 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
91 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
92 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
93 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634
94 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf
95 #define CONFIG_SYS_DDR_MODE_1 0x00440462
96 #define CONFIG_SYS_DDR_MODE_2 0x00000000
97 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100
98 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
99 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
100 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
101 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
102 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
103 #define CONFIG_SYS_DDR_CONTROL2 0x24400000
105 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
106 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
107 #define CONFIG_SYS_DDR_SBE 0x00010000
110 * Make sure required options are set
112 #ifndef CONFIG_SPD_EEPROM
113 #error ("CONFIG_SPD_EEPROM is required")
119 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
120 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
121 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
122 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
124 * Localbus cacheable (TBD)
125 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
127 * Localbus non-cacheable
128 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
129 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
130 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
131 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
132 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
133 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
137 * Local Bus Definitions
139 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
140 #ifdef CONFIG_PHYS_64BIT
141 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
143 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
146 #define CONFIG_FLASH_BR_PRELIM \
147 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
148 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
150 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
151 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
153 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
154 #define CONFIG_SYS_FLASH_QUIET_TEST
155 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
157 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
158 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
159 #undef CONFIG_SYS_FLASH_CHECKSUM
160 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
161 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
163 #undef CONFIG_SYS_RAMBOOT
165 #define CONFIG_SYS_FLASH_EMPTY_INFO
166 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
168 #define CONFIG_HWCONFIG /* enable hwconfig */
169 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
170 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
171 #ifdef CONFIG_PHYS_64BIT
172 #define PIXIS_BASE_PHYS 0xfffdf0000ull
174 #define PIXIS_BASE_PHYS PIXIS_BASE
177 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
178 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
180 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
181 #define PIXIS_VER 0x1 /* Board version at offset 1 */
182 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
183 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
184 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
185 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
186 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
187 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
188 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
189 #define PIXIS_VCTL 0x10 /* VELA Control Register */
190 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
191 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
192 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
193 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
194 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
195 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
196 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
197 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
198 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
199 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
200 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
201 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
202 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
203 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
204 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
205 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
206 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
207 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
208 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
209 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
210 #define PIXIS_LED 0x25 /* LED Register */
212 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
214 /* old pixis referenced names */
215 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
216 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
217 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
218 #define PIXIS_VSPEED2_TSEC1SER 0x8
219 #define PIXIS_VSPEED2_TSEC2SER 0x4
220 #define PIXIS_VSPEED2_TSEC3SER 0x2
221 #define PIXIS_VSPEED2_TSEC4SER 0x1
222 #define PIXIS_VCFGEN1_TSEC1SER 0x20
223 #define PIXIS_VCFGEN1_TSEC2SER 0x20
224 #define PIXIS_VCFGEN1_TSEC3SER 0x20
225 #define PIXIS_VCFGEN1_TSEC4SER 0x20
226 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
227 | PIXIS_VSPEED2_TSEC2SER \
228 | PIXIS_VSPEED2_TSEC3SER \
229 | PIXIS_VSPEED2_TSEC4SER)
230 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
231 | PIXIS_VCFGEN1_TSEC2SER \
232 | PIXIS_VCFGEN1_TSEC3SER \
233 | PIXIS_VCFGEN1_TSEC4SER)
235 #define CONFIG_SYS_INIT_RAM_LOCK 1
236 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
237 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
239 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
240 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
242 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
243 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
245 #ifndef CONFIG_NAND_SPL
246 #define CONFIG_SYS_NAND_BASE 0xffa00000
247 #ifdef CONFIG_PHYS_64BIT
248 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
250 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
253 #define CONFIG_SYS_NAND_BASE 0xfff00000
254 #ifdef CONFIG_PHYS_64BIT
255 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
257 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
261 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
262 CONFIG_SYS_NAND_BASE + 0x40000, \
263 CONFIG_SYS_NAND_BASE + 0x80000,\
264 CONFIG_SYS_NAND_BASE + 0xC0000}
265 #define CONFIG_SYS_MAX_NAND_DEVICE 4
266 #define CONFIG_NAND_FSL_ELBC 1
267 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
268 #define CONFIG_SYS_NAND_MAX_OOBFREE 5
269 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
271 /* NAND boot: 4K NAND loader config */
272 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
273 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
274 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
275 #define CONFIG_SYS_NAND_U_BOOT_START \
276 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
277 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
278 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
279 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
281 /* NAND flash config */
282 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
283 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
284 | BR_PS_8 /* Port Size = 8 bit */ \
285 | BR_MS_FCM /* MSEL = FCM */ \
287 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
288 | OR_FCM_PGS /* Large Page*/ \
296 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
297 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
298 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
299 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
300 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
301 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
302 | BR_PS_8 /* Port Size = 8 bit */ \
303 | BR_MS_FCM /* MSEL = FCM */ \
305 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
306 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
307 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
308 | BR_PS_8 /* Port Size = 8 bit */ \
309 | BR_MS_FCM /* MSEL = FCM */ \
311 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
313 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
314 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
315 | BR_PS_8 /* Port Size = 8 bit */ \
316 | BR_MS_FCM /* MSEL = FCM */ \
318 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
320 /* Serial Port - controlled on board with jumper J8
324 #define CONFIG_SYS_NS16550_SERIAL
325 #define CONFIG_SYS_NS16550_REG_SIZE 1
326 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
327 #ifdef CONFIG_NAND_SPL
328 #define CONFIG_NS16550_MIN_FUNCTIONS
331 #define CONFIG_SYS_BAUDRATE_TABLE \
332 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
334 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
335 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
338 #define CONFIG_SYS_I2C
339 #define CONFIG_SYS_I2C_FSL
340 #define CONFIG_SYS_FSL_I2C_SPEED 400000
341 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
342 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
343 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
344 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
345 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
346 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
347 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
352 #define CONFIG_ID_EEPROM
353 #ifdef CONFIG_ID_EEPROM
354 #define CONFIG_SYS_I2C_EEPROM_NXID
356 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
357 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
358 #define CONFIG_SYS_EEPROM_BUS_NUM 1
362 * Memory space is mapped 1-1, but I/O space must start from 0.
365 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
366 #define CONFIG_SYS_PCIE3_NAME "ULI"
367 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
368 #ifdef CONFIG_PHYS_64BIT
369 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
370 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
372 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
373 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
375 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
376 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
377 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
378 #ifdef CONFIG_PHYS_64BIT
379 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
381 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
383 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
385 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
386 #define CONFIG_SYS_PCIE2_NAME "Slot 1"
387 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
388 #ifdef CONFIG_PHYS_64BIT
389 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
390 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
392 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
393 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
395 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
396 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
397 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
398 #ifdef CONFIG_PHYS_64BIT
399 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
401 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
403 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
405 /* controller 1, Slot 1, tgtid 1, Base address a000 */
406 #define CONFIG_SYS_PCIE1_NAME "Slot 2"
407 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
408 #ifdef CONFIG_PHYS_64BIT
409 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
410 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
412 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
413 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
415 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
416 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
417 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
418 #ifdef CONFIG_PHYS_64BIT
419 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
421 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
423 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
425 #if defined(CONFIG_PCI)
427 /*PCIE video card used*/
428 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
432 #if defined(CONFIG_VIDEO)
433 #define CONFIG_BIOSEMU
434 #define CONFIG_ATI_RADEON_FB
435 #define CONFIG_VIDEO_LOGO
436 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
440 #ifndef CONFIG_PCI_PNP
441 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
442 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
443 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
446 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
448 #ifdef CONFIG_SCSI_AHCI
449 #define CONFIG_SATA_ULI5288
450 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
451 #define CONFIG_SYS_SCSI_MAX_LUN 1
452 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
455 #endif /* CONFIG_PCI */
457 #if defined(CONFIG_TSEC_ENET)
459 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
460 #define CONFIG_TSEC1 1
461 #define CONFIG_TSEC1_NAME "eTSEC1"
462 #define CONFIG_TSEC2 1
463 #define CONFIG_TSEC2_NAME "eTSEC2"
464 #define CONFIG_TSEC3 1
465 #define CONFIG_TSEC3_NAME "eTSEC3"
466 #define CONFIG_TSEC4 1
467 #define CONFIG_TSEC4_NAME "eTSEC4"
469 #define CONFIG_PIXIS_SGMII_CMD
470 #define CONFIG_FSL_SGMII_RISER 1
471 #define SGMII_RISER_PHY_OFFSET 0x1c
473 #ifdef CONFIG_FSL_SGMII_RISER
474 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
477 #define TSEC1_PHY_ADDR 0
478 #define TSEC2_PHY_ADDR 1
479 #define TSEC3_PHY_ADDR 2
480 #define TSEC4_PHY_ADDR 3
482 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
483 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
484 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
485 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
487 #define TSEC1_PHYIDX 0
488 #define TSEC2_PHYIDX 0
489 #define TSEC3_PHYIDX 0
490 #define TSEC4_PHYIDX 0
492 #define CONFIG_ETHPRIME "eTSEC1"
493 #endif /* CONFIG_TSEC_ENET */
499 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
500 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
506 #ifdef CONFIG_USB_EHCI_HCD
507 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
508 #define CONFIG_PCI_EHCI_DEVICE 0
511 #undef CONFIG_WATCHDOG /* watchdog disabled */
514 * Miscellaneous configurable options
516 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
519 * For booting Linux, the board info and command line data
520 * have to be in the first 64 MB of memory, since this is
521 * the maximum mapped by the Linux kernel during initialization.
523 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
524 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
526 #if defined(CONFIG_CMD_KGDB)
527 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
531 * Environment Configuration
533 #if defined(CONFIG_TSEC_ENET)
534 #define CONFIG_HAS_ETH0
535 #define CONFIG_HAS_ETH1
536 #define CONFIG_HAS_ETH2
537 #define CONFIG_HAS_ETH3
540 #define CONFIG_IPADDR 192.168.1.254
542 #define CONFIG_HOSTNAME "unknown"
543 #define CONFIG_ROOTPATH "/opt/nfsroot"
544 #define CONFIG_BOOTFILE "uImage"
545 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
547 #define CONFIG_SERVERIP 192.168.1.1
548 #define CONFIG_GATEWAYIP 192.168.1.1
549 #define CONFIG_NETMASK 255.255.255.0
551 /* default location for tftp and bootm */
552 #define CONFIG_LOADADDR 1000000
554 #define CONFIG_EXTRA_ENV_SETTINGS \
555 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
557 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
558 "tftpflash=tftpboot $loadaddr $uboot; " \
559 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
561 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
563 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
565 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
567 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
569 "consoledev=ttyS0\0" \
570 "ramdiskaddr=2000000\0" \
571 "ramdiskfile=8572ds/ramdisk.uboot\0" \
572 "fdtaddr=1e00000\0" \
573 "fdtfile=8572ds/mpc8572ds.dtb\0" \
576 #define CONFIG_HDBOOT \
577 "setenv bootargs root=/dev/$bdev rw " \
578 "console=$consoledev,$baudrate $othbootargs;" \
579 "tftp $loadaddr $bootfile;" \
580 "tftp $fdtaddr $fdtfile;" \
581 "bootm $loadaddr - $fdtaddr"
583 #define CONFIG_NFSBOOTCOMMAND \
584 "setenv bootargs root=/dev/nfs rw " \
585 "nfsroot=$serverip:$rootpath " \
586 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
587 "console=$consoledev,$baudrate $othbootargs;" \
588 "tftp $loadaddr $bootfile;" \
589 "tftp $fdtaddr $fdtfile;" \
590 "bootm $loadaddr - $fdtaddr"
592 #define CONFIG_RAMBOOTCOMMAND \
593 "setenv bootargs root=/dev/ram rw " \
594 "console=$consoledev,$baudrate $othbootargs;" \
595 "tftp $ramdiskaddr $ramdiskfile;" \
596 "tftp $loadaddr $bootfile;" \
597 "tftp $fdtaddr $fdtfile;" \
598 "bootm $loadaddr $ramdiskaddr $fdtaddr"
600 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
602 #endif /* __CONFIG_H */