1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 * mpc8569mds board configuration file
12 #define CONFIG_SYS_SRIO
13 #define CONFIG_SRIO1 /* SRIO port 1 */
15 #define CONFIG_PCIE1 1 /* PCIE controller */
16 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
17 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
18 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
21 extern unsigned long get_clock_freq(void);
23 /* Replace a call to get_clock_freq (after it is implemented)*/
24 #define CONFIG_SYS_CLK_FREQ 66666666
25 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
28 #define CONFIG_PQ_MDS_PIB
29 #define CONFIG_PQ_MDS_PIB_ATM
33 * These can be toggled for performance analysis, otherwise use default.
35 #define CONFIG_L2_CACHE /* toggle L2 cache */
36 #define CONFIG_BTB /* toggle branch predition */
38 #ifndef CONFIG_SYS_MONITOR_BASE
39 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
43 * Only possible on E500 Version 2 or newer cores.
45 #define CONFIG_ENABLE_36BIT_PHYS 1
47 #define CONFIG_HWCONFIG
50 * Config the L2 Cache as L2 SRAM
52 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
53 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
54 #define CONFIG_SYS_L2_SIZE (512 << 10)
55 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
57 #define CONFIG_SYS_CCSRBAR 0xe0000000
58 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
60 #if defined(CONFIG_NAND_SPL)
61 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
65 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
66 #define CONFIG_DDR_SPD
67 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
69 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
71 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
72 /* DDR is system memory*/
73 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
75 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
76 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
78 /* I2C addresses of SPD EEPROMs */
79 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
81 /* These are used when DDR doesn't use SPD. */
82 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
83 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
84 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
85 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
86 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
87 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
88 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0
89 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
90 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
91 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
92 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
93 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
94 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
95 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
96 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
97 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
98 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
99 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
100 #define CONFIG_SYS_DDR_CDR_1 0x80040000
101 #define CONFIG_SYS_DDR_CDR_2 0x00000000
102 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
103 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
104 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */
105 #define CONFIG_SYS_DDR_CONTROL2 0x24400000
107 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
108 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
109 #define CONFIG_SYS_DDR_SBE 0x00010000
112 * Local Bus Definitions
115 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
116 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
118 #define CONFIG_SYS_BCSR_BASE 0xf8000000
119 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
121 /*Chip select 0 - Flash*/
122 #define CONFIG_FLASH_BR_PRELIM 0xfe000801
123 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
125 /*Chip select 1 - BCSR*/
126 #define CONFIG_SYS_BR1_PRELIM 0xf8000801
127 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
129 /*Chip select 4 - PIB*/
130 #define CONFIG_SYS_BR4_PRELIM 0xf8008801
131 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
133 /*Chip select 5 - PIB*/
134 #define CONFIG_SYS_BR5_PRELIM 0xf8010801
135 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
137 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
138 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
139 #undef CONFIG_SYS_FLASH_CHECKSUM
140 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
141 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
143 #undef CONFIG_SYS_RAMBOOT
145 #define CONFIG_SYS_FLASH_EMPTY_INFO
147 /* Chip select 3 - NAND */
148 #ifndef CONFIG_NAND_SPL
149 #define CONFIG_SYS_NAND_BASE 0xFC000000
151 #define CONFIG_SYS_NAND_BASE 0xFFF00000
154 /* NAND boot: 4K NAND loader config */
155 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
156 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
157 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
158 #define CONFIG_SYS_NAND_U_BOOT_START \
159 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
160 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
161 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
162 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
164 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
165 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
166 #define CONFIG_SYS_MAX_NAND_DEVICE 1
167 #define CONFIG_NAND_FSL_ELBC 1
168 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
169 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
170 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
171 | BR_PS_8 /* Port Size = 8 bit */ \
172 | BR_MS_FCM /* MSEL = FCM */ \
174 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
182 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
183 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
184 #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
185 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
187 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
188 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
189 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
190 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
192 #define CONFIG_SYS_INIT_RAM_LOCK 1
193 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
194 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
196 #define CONFIG_SYS_GBL_DATA_OFFSET \
197 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
198 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
200 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
201 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
204 #define CONFIG_SYS_NS16550_SERIAL
205 #define CONFIG_SYS_NS16550_REG_SIZE 1
206 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
207 #ifdef CONFIG_NAND_SPL
208 #define CONFIG_NS16550_MIN_FUNCTIONS
211 #define CONFIG_SYS_BAUDRATE_TABLE \
212 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
214 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
215 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
220 #define CONFIG_SYS_I2C
221 #define CONFIG_SYS_I2C_FSL
222 #define CONFIG_SYS_FSL_I2C_SPEED 400000
223 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
224 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
225 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
226 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
227 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
228 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
233 #define CONFIG_ID_EEPROM
234 #ifdef CONFIG_ID_EEPROM
235 #define CONFIG_SYS_I2C_EEPROM_NXID
237 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
238 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
239 #define CONFIG_SYS_EEPROM_BUS_NUM 1
241 #define PLPPAR1_I2C_BIT_MASK 0x0000000F
242 #define PLPPAR1_I2C2_VAL 0x00000000
243 #define PLPPAR1_ESDHC_VAL 0x0000000A
244 #define PLPDIR1_I2C_BIT_MASK 0x0000000F
245 #define PLPDIR1_I2C2_VAL 0x0000000F
246 #define PLPDIR1_ESDHC_VAL 0x00000006
247 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0
248 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
249 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0
250 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
254 * Memory Addresses are mapped 1-1. I/O is mapped from 0
256 #define CONFIG_SYS_PCIE1_NAME "Slot"
257 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
258 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
259 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
260 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
261 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
262 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
263 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
264 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
266 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
267 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
268 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
269 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
273 * QE UEC ethernet configuration
275 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */
276 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */
278 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
279 #define CONFIG_UEC_ETH
280 #define CONFIG_ETHPRIME "UEC0"
281 #define CONFIG_PHY_MODE_NEED_CHANGE
283 #define CONFIG_UEC_ETH1 /* GETH1 */
284 #define CONFIG_HAS_ETH0
286 #ifdef CONFIG_UEC_ETH1
287 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
288 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
289 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
290 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
291 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
292 #define CONFIG_SYS_UEC1_PHY_ADDR 7
293 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
294 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
295 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
296 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
297 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
298 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
299 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
300 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
301 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
302 #endif /* CONFIG_UEC_ETH1 */
304 #define CONFIG_UEC_ETH2 /* GETH2 */
305 #define CONFIG_HAS_ETH1
307 #ifdef CONFIG_UEC_ETH2
308 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
309 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
310 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
311 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
312 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
313 #define CONFIG_SYS_UEC2_PHY_ADDR 1
314 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
315 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
316 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
317 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
318 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
319 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
320 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
321 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
322 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
323 #endif /* CONFIG_UEC_ETH2 */
325 #define CONFIG_UEC_ETH3 /* GETH3 */
326 #define CONFIG_HAS_ETH2
328 #ifdef CONFIG_UEC_ETH3
329 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */
330 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
331 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
332 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
333 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
334 #define CONFIG_SYS_UEC3_PHY_ADDR 2
335 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
336 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
337 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
338 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
339 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
340 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
341 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
342 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
343 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
344 #endif /* CONFIG_UEC_ETH3 */
346 #define CONFIG_UEC_ETH4 /* GETH4 */
347 #define CONFIG_HAS_ETH3
349 #ifdef CONFIG_UEC_ETH4
350 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */
351 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
352 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
353 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
354 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
355 #define CONFIG_SYS_UEC4_PHY_ADDR 3
356 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
357 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
358 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
359 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
360 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
361 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
362 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
363 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
364 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
365 #endif /* CONFIG_UEC_ETH4 */
367 #undef CONFIG_UEC_ETH6 /* GETH6 */
368 #define CONFIG_HAS_ETH5
370 #ifdef CONFIG_UEC_ETH6
371 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */
372 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
373 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
374 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
375 #define CONFIG_SYS_UEC6_PHY_ADDR 4
376 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
377 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
378 #endif /* CONFIG_UEC_ETH6 */
380 #undef CONFIG_UEC_ETH8 /* GETH8 */
381 #define CONFIG_HAS_ETH7
383 #ifdef CONFIG_UEC_ETH8
384 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */
385 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
386 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
387 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
388 #define CONFIG_SYS_UEC8_PHY_ADDR 6
389 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
390 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
391 #endif /* CONFIG_UEC_ETH8 */
393 #endif /* CONFIG_QE */
395 #if defined(CONFIG_PCI)
397 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
399 #endif /* CONFIG_PCI */
405 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
406 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
408 /* QE microcode/firmware address */
409 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000
414 #define CONFIG_BOOTP_BOOTFILESIZE
416 #undef CONFIG_WATCHDOG /* watchdog disabled */
419 #define CONFIG_FSL_ESDHC_PIN_MUX
420 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
424 * Miscellaneous configurable options
426 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
427 #if defined(CONFIG_CMD_KGDB)
428 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */
430 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
432 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
433 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
434 /* Boot Argument Buffer Size */
437 * For booting Linux, the board info and command line data
438 * have to be in the first 64 MB of memory, since this is
439 * the maximum mapped by the Linux kernel during initialization.
441 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
442 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
444 #if defined(CONFIG_CMD_KGDB)
445 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
449 * Environment Configuration
451 #define CONFIG_HOSTNAME "mpc8569mds"
452 #define CONFIG_ROOTPATH "/nfsroot"
453 #define CONFIG_BOOTFILE "your.uImage"
455 #define CONFIG_SERVERIP 192.168.1.1
456 #define CONFIG_GATEWAYIP 192.168.1.1
457 #define CONFIG_NETMASK 255.255.255.0
459 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
461 #define CONFIG_EXTRA_ENV_SETTINGS \
463 "consoledev=ttyS0\0" \
464 "ramdiskaddr=600000\0" \
465 "ramdiskfile=your.ramdisk.u-boot\0" \
467 "fdtfile=your.fdt.dtb\0" \
468 "nfsargs=setenv bootargs root=/dev/nfs rw " \
469 "nfsroot=$serverip:$rootpath " \
470 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
471 "console=$consoledev,$baudrate $othbootargs\0" \
472 "ramargs=setenv bootargs root=/dev/ram rw " \
473 "console=$consoledev,$baudrate $othbootargs\0" \
475 #define CONFIG_NFSBOOTCOMMAND \
477 "tftp $loadaddr $bootfile;" \
478 "tftp $fdtaddr $fdtfile;" \
479 "bootm $loadaddr - $fdtaddr"
481 #define CONFIG_RAMBOOTCOMMAND \
483 "tftp $ramdiskaddr $ramdiskfile;" \
484 "tftp $loadaddr $bootfile;" \
485 "bootm $loadaddr $ramdiskaddr"
487 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
489 #endif /* __CONFIG_H */