2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * mpc8569mds board configuration file
13 /* High Level Configuration Options */
14 #define CONFIG_BOOKE 1 /* BOOKE */
15 #define CONFIG_E500 1 /* BOOKE e500 family */
16 #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */
18 #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */
20 #define CONFIG_SYS_SRIO
21 #define CONFIG_SRIO1 /* SRIO port 1 */
23 #define CONFIG_PCIE1 1 /* PCIE controller */
24 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
25 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
26 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
27 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
28 #define CONFIG_QE /* Enable QE */
29 #define CONFIG_ENV_OVERWRITE
30 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
33 extern unsigned long get_clock_freq(void);
35 /* Replace a call to get_clock_freq (after it is implemented)*/
36 #define CONFIG_SYS_CLK_FREQ 66666666
37 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
40 #define CONFIG_PQ_MDS_PIB
41 #define CONFIG_PQ_MDS_PIB_ATM
45 * These can be toggled for performance analysis, otherwise use default.
47 #define CONFIG_L2_CACHE /* toggle L2 cache */
48 #define CONFIG_BTB /* toggle branch predition */
50 #ifndef CONFIG_SYS_TEXT_BASE
51 #define CONFIG_SYS_TEXT_BASE 0xfff80000
54 #ifndef CONFIG_SYS_MONITOR_BASE
55 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
59 * Only possible on E500 Version 2 or newer cores.
61 #define CONFIG_ENABLE_36BIT_PHYS 1
63 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
64 #define CONFIG_BOARD_EARLY_INIT_R 1
65 #define CONFIG_HWCONFIG
67 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
68 #define CONFIG_SYS_MEMTEST_END 0x00400000
71 * Config the L2 Cache as L2 SRAM
73 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
74 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
75 #define CONFIG_SYS_L2_SIZE (512 << 10)
76 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
78 #define CONFIG_SYS_CCSRBAR 0xe0000000
79 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
81 #if defined(CONFIG_NAND_SPL)
82 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
86 #define CONFIG_SYS_FSL_DDR3
87 #undef CONFIG_FSL_DDR_INTERACTIVE
88 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
89 #define CONFIG_DDR_SPD
90 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
92 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
94 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
95 /* DDR is system memory*/
96 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
98 #define CONFIG_NUM_DDR_CONTROLLERS 1
99 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
100 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
102 /* I2C addresses of SPD EEPROMs */
103 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
105 /* These are used when DDR doesn't use SPD. */
106 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
107 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
108 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
109 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
110 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
111 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
112 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0
113 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
114 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
115 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
116 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
117 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
118 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
119 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
120 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
121 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
122 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
123 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
124 #define CONFIG_SYS_DDR_CDR_1 0x80040000
125 #define CONFIG_SYS_DDR_CDR_2 0x00000000
126 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
127 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
128 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */
129 #define CONFIG_SYS_DDR_CONTROL2 0x24400000
131 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
132 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
133 #define CONFIG_SYS_DDR_SBE 0x00010000
135 #undef CONFIG_CLOCKS_IN_MHZ
138 * Local Bus Definitions
141 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
142 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
144 #define CONFIG_SYS_BCSR_BASE 0xf8000000
145 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
147 /*Chip select 0 - Flash*/
148 #define CONFIG_FLASH_BR_PRELIM 0xfe000801
149 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
151 /*Chip select 1 - BCSR*/
152 #define CONFIG_SYS_BR1_PRELIM 0xf8000801
153 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
155 /*Chip select 4 - PIB*/
156 #define CONFIG_SYS_BR4_PRELIM 0xf8008801
157 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
159 /*Chip select 5 - PIB*/
160 #define CONFIG_SYS_BR5_PRELIM 0xf8010801
161 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
163 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
164 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
165 #undef CONFIG_SYS_FLASH_CHECKSUM
166 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
167 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
169 #undef CONFIG_SYS_RAMBOOT
171 #define CONFIG_FLASH_CFI_DRIVER
172 #define CONFIG_SYS_FLASH_CFI
173 #define CONFIG_SYS_FLASH_EMPTY_INFO
175 /* Chip select 3 - NAND */
176 #ifndef CONFIG_NAND_SPL
177 #define CONFIG_SYS_NAND_BASE 0xFC000000
179 #define CONFIG_SYS_NAND_BASE 0xFFF00000
182 /* NAND boot: 4K NAND loader config */
183 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
184 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
185 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
186 #define CONFIG_SYS_NAND_U_BOOT_START \
187 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
188 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
189 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
190 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
192 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
193 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
194 #define CONFIG_SYS_MAX_NAND_DEVICE 1
195 #define CONFIG_CMD_NAND 1
196 #define CONFIG_NAND_FSL_ELBC 1
197 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
198 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
199 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
200 | BR_PS_8 /* Port Size = 8 bit */ \
201 | BR_MS_FCM /* MSEL = FCM */ \
203 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
211 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
212 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
213 #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
214 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
216 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
217 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
218 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
219 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
221 #define CONFIG_SYS_INIT_RAM_LOCK 1
222 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
223 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
225 #define CONFIG_SYS_GBL_DATA_OFFSET \
226 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
227 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
229 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
230 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
233 #define CONFIG_CONS_INDEX 1
234 #define CONFIG_SYS_NS16550_SERIAL
235 #define CONFIG_SYS_NS16550_REG_SIZE 1
236 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
237 #ifdef CONFIG_NAND_SPL
238 #define CONFIG_NS16550_MIN_FUNCTIONS
241 #define CONFIG_SYS_BAUDRATE_TABLE \
242 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
244 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
245 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
250 #define CONFIG_SYS_I2C
251 #define CONFIG_SYS_I2C_FSL
252 #define CONFIG_SYS_FSL_I2C_SPEED 400000
253 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
254 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
255 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
256 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
257 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
258 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
263 #define CONFIG_ID_EEPROM
264 #ifdef CONFIG_ID_EEPROM
265 #define CONFIG_SYS_I2C_EEPROM_NXID
267 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
268 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
269 #define CONFIG_SYS_EEPROM_BUS_NUM 1
271 #define PLPPAR1_I2C_BIT_MASK 0x0000000F
272 #define PLPPAR1_I2C2_VAL 0x00000000
273 #define PLPPAR1_ESDHC_VAL 0x0000000A
274 #define PLPDIR1_I2C_BIT_MASK 0x0000000F
275 #define PLPDIR1_I2C2_VAL 0x0000000F
276 #define PLPDIR1_ESDHC_VAL 0x00000006
277 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0
278 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
279 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0
280 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
284 * Memory Addresses are mapped 1-1. I/O is mapped from 0
286 #define CONFIG_SYS_PCIE1_NAME "Slot"
287 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
288 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
289 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
290 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
291 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
292 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
293 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
294 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
296 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
297 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
298 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
299 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
303 * QE UEC ethernet configuration
305 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */
306 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */
308 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
309 #define CONFIG_UEC_ETH
310 #define CONFIG_ETHPRIME "UEC0"
311 #define CONFIG_PHY_MODE_NEED_CHANGE
313 #define CONFIG_UEC_ETH1 /* GETH1 */
314 #define CONFIG_HAS_ETH0
316 #ifdef CONFIG_UEC_ETH1
317 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
318 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
319 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
320 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
321 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
322 #define CONFIG_SYS_UEC1_PHY_ADDR 7
323 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
324 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
325 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
326 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
327 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
328 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
329 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
330 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
331 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
332 #endif /* CONFIG_UEC_ETH1 */
334 #define CONFIG_UEC_ETH2 /* GETH2 */
335 #define CONFIG_HAS_ETH1
337 #ifdef CONFIG_UEC_ETH2
338 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
339 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
340 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
341 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
342 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
343 #define CONFIG_SYS_UEC2_PHY_ADDR 1
344 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
345 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
346 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
347 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
348 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
349 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
350 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
351 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
352 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
353 #endif /* CONFIG_UEC_ETH2 */
355 #define CONFIG_UEC_ETH3 /* GETH3 */
356 #define CONFIG_HAS_ETH2
358 #ifdef CONFIG_UEC_ETH3
359 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */
360 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
361 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
362 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
363 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
364 #define CONFIG_SYS_UEC3_PHY_ADDR 2
365 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
366 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
367 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
368 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
369 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
370 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
371 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
372 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
373 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
374 #endif /* CONFIG_UEC_ETH3 */
376 #define CONFIG_UEC_ETH4 /* GETH4 */
377 #define CONFIG_HAS_ETH3
379 #ifdef CONFIG_UEC_ETH4
380 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */
381 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
382 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
383 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
384 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
385 #define CONFIG_SYS_UEC4_PHY_ADDR 3
386 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
387 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
388 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
389 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
390 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
391 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
392 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
393 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
394 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
395 #endif /* CONFIG_UEC_ETH4 */
397 #undef CONFIG_UEC_ETH6 /* GETH6 */
398 #define CONFIG_HAS_ETH5
400 #ifdef CONFIG_UEC_ETH6
401 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */
402 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
403 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
404 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
405 #define CONFIG_SYS_UEC6_PHY_ADDR 4
406 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
407 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
408 #endif /* CONFIG_UEC_ETH6 */
410 #undef CONFIG_UEC_ETH8 /* GETH8 */
411 #define CONFIG_HAS_ETH7
413 #ifdef CONFIG_UEC_ETH8
414 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */
415 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
416 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
417 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
418 #define CONFIG_SYS_UEC8_PHY_ADDR 6
419 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
420 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
421 #endif /* CONFIG_UEC_ETH8 */
423 #endif /* CONFIG_QE */
425 #if defined(CONFIG_PCI)
426 #undef CONFIG_EEPRO100
429 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
431 #endif /* CONFIG_PCI */
436 #if defined(CONFIG_SYS_RAMBOOT)
438 #define CONFIG_ENV_IS_IN_FLASH 1
439 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
440 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
441 #define CONFIG_ENV_SIZE 0x2000
444 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
445 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
447 /* QE microcode/firmware address */
448 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
449 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000
454 #define CONFIG_BOOTP_BOOTFILESIZE
455 #define CONFIG_BOOTP_BOOTPATH
456 #define CONFIG_BOOTP_GATEWAY
457 #define CONFIG_BOOTP_HOSTNAME
460 * Command line configuration.
462 #define CONFIG_CMD_IRQ
463 #define CONFIG_CMD_REGINFO
465 #if defined(CONFIG_PCI)
466 #define CONFIG_CMD_PCI
469 #undef CONFIG_WATCHDOG /* watchdog disabled */
474 #define CONFIG_FSL_ESDHC
475 #define CONFIG_FSL_ESDHC_PIN_MUX
476 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
477 #define CONFIG_GENERIC_MMC
478 #define CONFIG_DOS_PARTITION
482 * Miscellaneous configurable options
484 #define CONFIG_SYS_LONGHELP /* undef to save memory */
485 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
486 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
487 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
488 #if defined(CONFIG_CMD_KGDB)
489 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */
491 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
493 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
494 /* Print Buffer Size */
495 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
496 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
497 /* Boot Argument Buffer Size */
500 * For booting Linux, the board info and command line data
501 * have to be in the first 64 MB of memory, since this is
502 * the maximum mapped by the Linux kernel during initialization.
504 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
505 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
507 #if defined(CONFIG_CMD_KGDB)
508 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
512 * Environment Configuration
514 #define CONFIG_HOSTNAME mpc8569mds
515 #define CONFIG_ROOTPATH "/nfsroot"
516 #define CONFIG_BOOTFILE "your.uImage"
518 #define CONFIG_SERVERIP 192.168.1.1
519 #define CONFIG_GATEWAYIP 192.168.1.1
520 #define CONFIG_NETMASK 255.255.255.0
522 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
524 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
526 #define CONFIG_BAUDRATE 115200
528 #define CONFIG_EXTRA_ENV_SETTINGS \
530 "consoledev=ttyS0\0" \
531 "ramdiskaddr=600000\0" \
532 "ramdiskfile=your.ramdisk.u-boot\0" \
534 "fdtfile=your.fdt.dtb\0" \
535 "nfsargs=setenv bootargs root=/dev/nfs rw " \
536 "nfsroot=$serverip:$rootpath " \
537 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
538 "console=$consoledev,$baudrate $othbootargs\0" \
539 "ramargs=setenv bootargs root=/dev/ram rw " \
540 "console=$consoledev,$baudrate $othbootargs\0" \
542 #define CONFIG_NFSBOOTCOMMAND \
544 "tftp $loadaddr $bootfile;" \
545 "tftp $fdtaddr $fdtfile;" \
546 "bootm $loadaddr - $fdtaddr"
548 #define CONFIG_RAMBOOTCOMMAND \
550 "tftp $ramdiskaddr $ramdiskfile;" \
551 "tftp $loadaddr $bootfile;" \
552 "bootm $loadaddr $ramdiskaddr"
554 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
556 #endif /* __CONFIG_H */