1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
7 * mpc8568mds board configuration file
12 #define CONFIG_SYS_SRIO
13 #define CONFIG_SRIO1 /* SRIO port 1 */
15 #define CONFIG_PCI1 1 /* PCI controller */
16 #define CONFIG_PCIE1 1 /* PCIE controller */
17 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
18 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
19 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
20 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
21 #define CONFIG_QE /* Enable QE */
22 #define CONFIG_ENV_OVERWRITE
25 extern unsigned long get_clock_freq(void);
26 #endif /*Replace a call to get_clock_freq (after it is implemented)*/
27 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
30 * These can be toggled for performance analysis, otherwise use default.
32 #define CONFIG_L2_CACHE /* toggle L2 cache */
33 #define CONFIG_BTB /* toggle branch predition */
36 * Only possible on E500 Version 2 or newer cores.
38 #define CONFIG_ENABLE_36BIT_PHYS 1
40 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
41 #define CONFIG_SYS_MEMTEST_END 0x00400000
43 #define CONFIG_SYS_CCSRBAR 0xe0000000
44 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
47 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
48 #define CONFIG_DDR_SPD
49 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
51 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
53 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
54 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
56 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
57 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
59 /* I2C addresses of SPD EEPROMs */
60 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
62 /* Make sure required options are set */
63 #ifndef CONFIG_SPD_EEPROM
64 #error ("CONFIG_SPD_EEPROM is required")
67 #undef CONFIG_CLOCKS_IN_MHZ
70 * Local Bus Definitions
74 * FLASH on the Local Bus
75 * Two banks, 8M each, using the CFI driver.
76 * Boot from BR0/OR0 bank at 0xff00_0000
77 * Alternate BR1/OR1 bank at 0xff80_0000
80 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
81 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
82 * Port Size = 16 bits = BRx[19:20] = 10
83 * Use GPCM = BRx[24:26] = 000
86 * 0 4 8 12 16 20 24 28
87 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
88 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
91 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
92 * Reserved ORx[17:18] = 11, confusion here?
94 * ACS = half cycle delay = ORx[21:22] = 11
95 * SCY = 6 = ORx[24:27] = 0110
96 * TRLX = use relaxed timing = ORx[29] = 1
97 * EAD = use external address latch delay = OR[31] = 1
99 * 0 4 8 12 16 20 24 28
100 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
102 #define CONFIG_SYS_BCSR_BASE 0xf8000000
104 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
106 /*Chip select 0 - Flash*/
107 #define CONFIG_SYS_BR0_PRELIM 0xfe001001
108 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7
110 /*Chip slelect 1 - BCSR*/
111 #define CONFIG_SYS_BR1_PRELIM 0xf8000801
112 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
114 /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */
115 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
116 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
117 #undef CONFIG_SYS_FLASH_CHECKSUM
118 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
119 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
121 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
123 #define CONFIG_SYS_FLASH_EMPTY_INFO
126 * SDRAM on the LocalBus
128 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
129 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
131 /*Chip select 2 - SDRAM*/
132 #define CONFIG_SYS_BR2_PRELIM 0xf0001861
133 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
135 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
136 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
137 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
138 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
141 * Common settings for all Local Bus SDRAM commands.
142 * At run time, either BSMA1516 (for CPU 1.1)
143 * or BSMA1617 (for CPU 1.0) (old)
146 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
156 * The bcsr registers are connected to CS3 on MDS.
157 * The new memory map places bcsr at 0xf8000000.
160 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
161 * port-size = 8-bits = BR[19:20] = 01
162 * no parity checking = BR[21:22] = 00
163 * GPMC for MSEL = BR[24:26] = 000
166 * 0 4 8 12 16 20 24 28
167 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
170 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
171 * disable buffer ctrl OR[19] = 0
175 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
179 * EAD extra time OR[31] = 1
181 * 0 4 8 12 16 20 24 28
182 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
184 #define CONFIG_SYS_BCSR (0xf8000000)
186 /*Chip slelect 4 - PIB*/
187 #define CONFIG_SYS_BR4_PRELIM 0xf8008801
188 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
190 /*Chip select 5 - PIB*/
191 #define CONFIG_SYS_BR5_PRELIM 0xf8010801
192 #define CONFIG_SYS_OR5_PRELIM 0xffff69f7
194 #define CONFIG_SYS_INIT_RAM_LOCK 1
195 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
196 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
198 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
199 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
201 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
202 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
205 #define CONFIG_SYS_NS16550_SERIAL
206 #define CONFIG_SYS_NS16550_REG_SIZE 1
207 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
209 #define CONFIG_SYS_BAUDRATE_TABLE \
210 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
212 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
213 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
218 #define CONFIG_SYS_I2C
219 #define CONFIG_SYS_I2C_FSL
220 #define CONFIG_SYS_FSL_I2C_SPEED 400000
221 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
222 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
223 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
224 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
225 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
226 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
227 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
231 * Memory Addresses are mapped 1-1. I/O is mapped from 0
233 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
234 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
235 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
236 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
237 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
238 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
239 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
240 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
242 #define CONFIG_SYS_PCIE1_NAME "Slot"
243 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
244 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
245 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
246 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
247 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
248 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
249 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
250 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
252 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
253 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
254 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
255 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
259 * QE UEC ethernet configuration
261 #define CONFIG_UEC_ETH
262 #ifndef CONFIG_TSEC_ENET
263 #define CONFIG_ETHPRIME "UEC0"
265 #define CONFIG_PHY_MODE_NEED_CHANGE
266 #define CONFIG_eTSEC_MDIO_BUS
268 #ifdef CONFIG_eTSEC_MDIO_BUS
269 #define CONFIG_MIIM_ADDRESS 0xE0024520
272 #define CONFIG_UEC_ETH1 /* GETH1 */
274 #ifdef CONFIG_UEC_ETH1
275 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
276 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
277 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
278 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
279 #define CONFIG_SYS_UEC1_PHY_ADDR 7
280 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
281 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
284 #define CONFIG_UEC_ETH2 /* GETH2 */
286 #ifdef CONFIG_UEC_ETH2
287 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
288 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
289 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
290 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
291 #define CONFIG_SYS_UEC2_PHY_ADDR 1
292 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
293 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
295 #endif /* CONFIG_QE */
297 #if defined(CONFIG_PCI)
298 #undef CONFIG_EEPRO100
301 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
302 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
304 #endif /* CONFIG_PCI */
306 #if defined(CONFIG_TSEC_ENET)
308 #define CONFIG_TSEC1 1
309 #define CONFIG_TSEC1_NAME "eTSEC0"
310 #define CONFIG_TSEC2 1
311 #define CONFIG_TSEC2_NAME "eTSEC1"
313 #define TSEC1_PHY_ADDR 2
314 #define TSEC2_PHY_ADDR 3
316 #define TSEC1_PHYIDX 0
317 #define TSEC2_PHYIDX 0
319 #define TSEC1_FLAGS TSEC_GIGABIT
320 #define TSEC2_FLAGS TSEC_GIGABIT
322 /* Options are: eTSEC[0-1] */
323 #define CONFIG_ETHPRIME "eTSEC0"
325 #endif /* CONFIG_TSEC_ENET */
330 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
331 #define CONFIG_ENV_SIZE 0x2000
332 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
334 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
335 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
340 #define CONFIG_BOOTP_BOOTFILESIZE
342 #undef CONFIG_WATCHDOG /* watchdog disabled */
345 * Miscellaneous configurable options
347 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
350 * For booting Linux, the board info and command line data
351 * have to be in the first 64 MB of memory, since this is
352 * the maximum mapped by the Linux kernel during initialization.
354 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
355 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
357 #if defined(CONFIG_CMD_KGDB)
358 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
362 * Environment Configuration
365 /* The mac addresses for all ethernet interface */
366 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
367 #define CONFIG_HAS_ETH0
368 #define CONFIG_HAS_ETH1
369 #define CONFIG_HAS_ETH2
370 #define CONFIG_HAS_ETH3
373 #define CONFIG_IPADDR 192.168.1.253
375 #define CONFIG_HOSTNAME "unknown"
376 #define CONFIG_ROOTPATH "/nfsroot"
377 #define CONFIG_BOOTFILE "your.uImage"
379 #define CONFIG_SERVERIP 192.168.1.1
380 #define CONFIG_GATEWAYIP 192.168.1.1
381 #define CONFIG_NETMASK 255.255.255.0
383 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
385 #define CONFIG_EXTRA_ENV_SETTINGS \
387 "consoledev=ttyS0\0" \
388 "ramdiskaddr=600000\0" \
389 "ramdiskfile=your.ramdisk.u-boot\0" \
391 "fdtfile=your.fdt.dtb\0" \
392 "nfsargs=setenv bootargs root=/dev/nfs rw " \
393 "nfsroot=$serverip:$rootpath " \
394 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
395 "console=$consoledev,$baudrate $othbootargs\0" \
396 "ramargs=setenv bootargs root=/dev/ram rw " \
397 "console=$consoledev,$baudrate $othbootargs\0" \
399 #define CONFIG_NFSBOOTCOMMAND \
401 "tftp $loadaddr $bootfile;" \
402 "tftp $fdtaddr $fdtfile;" \
403 "bootm $loadaddr - $fdtaddr"
405 #define CONFIG_RAMBOOTCOMMAND \
407 "tftp $ramdiskaddr $ramdiskfile;" \
408 "tftp $loadaddr $bootfile;" \
409 "bootm $loadaddr $ramdiskaddr"
411 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
413 #endif /* __CONFIG_H */