2 * (C) Copyright 2002,2003 Motorola,Inc.
3 * Xianghua Xiao <X.Xiao@motorola.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* mpc8560ads board configuration file */
25 /* please refer to doc/README.mpc85xx for more info */
26 /* make sure you change the MAC address and other network params first,
27 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
33 /* High Level Configuration Options */
34 #define CONFIG_BOOKE 1 /* BOOKE */
35 #define CONFIG_E500 1 /* BOOKE e500 family */
36 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
37 #define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
38 #define CONFIG_MPC8560 1 /* MPC8560 specific */
39 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
41 #undef CONFIG_PCI /* pci ethernet support */
42 #define CONFIG_TSEC_ENET /* tsec ethernet support */
43 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
44 #define CONFIG_ENV_OVERWRITE
45 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
46 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
48 #if defined(CONFIG_MPC85xx_REV1)
49 #define CONFIG_DDR_DLL /* possible DLL fix needed */
52 /* Using Localbus SDRAM to emulate flash before we can program the flash,
53 * normally you need a flash-boot image(u-boot.bin), if so undef this.
55 #undef CONFIG_RAM_AS_FLASH
57 #if !defined(CONFIG_PCI) /* some PCI card is 33Mhz only */
58 #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
60 #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
63 #if !defined(CONFIG_SPD_EEPROM) /* manually set up DDR parameters */
64 #define CONFIG_DDR_SETTING
67 /* below can be toggled for performance analysis. otherwise use default */
68 #define CONFIG_L2_CACHE /* toggle L2 cache */
69 #undef CONFIG_BTB /* toggle branch predition */
70 #undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
72 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
74 #undef CFG_DRAM_TEST /* memory test, takes time */
75 #define CFG_MEMTEST_START 0x00200000 /* memtest region */
76 #define CFG_MEMTEST_END 0x00400000
78 #if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
79 defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
80 defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
81 #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
85 * Base addresses -- Note these are effective addresses where the
86 * actual resources get mapped (not physical addresses)
88 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
89 #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
90 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
92 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
93 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
94 #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
96 #if defined(CONFIG_RAM_AS_FLASH)
97 #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
99 #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
101 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
103 #if defined(CONFIG_RAM_AS_FLASH)
104 #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
105 #define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
106 #else /* Boot from real Flash */
107 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
108 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
111 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
112 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
113 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */
114 #undef CFG_FLASH_CHECKSUM
115 #define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */
116 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
118 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
120 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
126 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
128 #if defined(CONFIG_DDR_SETTING)
129 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
130 #define CFG_DDR_CS0_CONFIG 0x80000002
131 #define CFG_DDR_TIMING_1 0x37344321
132 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning*/
133 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR*/
134 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
135 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page*/
138 #undef CONFIG_CLOCKS_IN_MHZ
140 /* local bus definitions */
141 #define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
142 #define CFG_OR2_PRELIM 0xfc006901
143 #define CFG_LBC_LCRR 0x00030004 /* local bus freq */
144 #define CFG_LBC_LBCR 0x00000000
145 #define CFG_LBC_LSRT 0x20000000
146 #define CFG_LBC_MRTPR 0x20000000
147 #define CFG_LBC_LSDMR_1 0x2861b723
148 #define CFG_LBC_LSDMR_2 0x0861b723
149 #define CFG_LBC_LSDMR_3 0x0861b723
150 #define CFG_LBC_LSDMR_4 0x1861b723
151 #define CFG_LBC_LSDMR_5 0x4061b723
153 #if defined(CONFIG_RAM_AS_FLASH)
154 #define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
156 #define CFG_BR4_PRELIM 0xfc000801 /* 32KB, 8-bit wide for ADS config reg */
158 #define CFG_OR4_PRELIM 0xffffe1f1
159 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
161 #define CONFIG_L1_INIT_RAM
162 #define CFG_INIT_RAM_LOCK 1
163 #define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
164 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
166 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
167 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
168 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
170 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
171 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
174 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
175 #undef CONFIG_CONS_NONE /* define if console on something else */
176 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
178 #define CONFIG_BAUDRATE 115200
180 #define CFG_BAUDRATE_TABLE \
181 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
183 /* Use the HUSH parser */
184 #define CFG_HUSH_PARSER
185 #ifdef CFG_HUSH_PARSER
186 #define CFG_PROMPT_HUSH_PS2 "> "
190 #define CONFIG_HARD_I2C /* I2C with hardware support*/
191 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
192 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
193 #define CFG_I2C_SLAVE 0x7F
194 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
196 #define CFG_PCI_MEM_BASE 0xe0000000
197 #define CFG_PCI_MEM_PHYS 0xe0000000
198 #define CFG_PCI_MEM_SIZE 0x10000000
200 #if defined(CONFIG_PCI) /* PCI Ethernet card */
201 #define CONFIG_NET_MULTI
202 #define CONFIG_EEPRO100
204 #define CONFIG_PCI_PNP /* do pci plug-and-play */
205 #if !defined(CONFIG_PCI_PNP)
206 #define PCI_ENET0_IOADDR 0xe0000000
207 #define PCI_ENET0_MEMADDR 0xe0000000
208 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
210 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
211 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
212 #if defined(CONFIG_MPC85xx_REV1) /* Errata PCI 7 */
213 #define CFG_PCI_SUBSYS_DEVICEID 0x0003
215 #define CFG_PCI_SUBSYS_DEVICEID 0x0009
217 #elif defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
218 #define CONFIG_NET_MULTI 1
219 #define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */
220 #define CONFIG_MII 1 /* MII PHY management */
221 #define CONFIG_PHY_ADDR 8 /* PHY address */
222 #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
223 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
224 #undef CONFIG_ETHER_NONE /* define if ether on something else */
225 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
226 #if (CONFIG_ETHER_INDEX == 2)
230 * - Select bus for bd/buffers
233 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
234 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
235 #define CFG_CPMFCR_RAMTYPE 0
236 #define CFG_FCC_PSMR (FCC_PSMR_FDE)
237 #define FETH2_RST 0x01
238 #elif (CONFIG_ETHER_INDEX == 3)
239 /* need more definitions here for FE3 */
240 #define FETH3_RST 0x80
241 #endif /* CONFIG_ETHER_INDEX */
242 #define CONFIG_MII /* MII PHY management */
243 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
245 * GPIO pins used for bit-banged MII communications
247 #define MDIO_PORT 2 /* Port C */
248 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
249 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
250 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
252 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
253 else iop->pdat &= ~0x00400000
255 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
256 else iop->pdat &= ~0x00200000
258 #define MIIDELAY udelay(1)
263 #if defined(CONFIG_RAM_AS_FLASH)
264 #define CFG_ENV_IS_NOWHERE
265 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
266 #define CFG_ENV_SIZE 0x2000
268 #define CFG_ENV_IS_IN_FLASH 1
269 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
270 #define CFG_ENV_SECT_SIZE 0x40000 /* 128K(one sector) for env */
272 #define CFG_ENV_SIZE 0x2000
274 #define CFG_NO_FLASH 1 /* Flash is not usable now */
275 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
276 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
277 #define CFG_ENV_SIZE 0x2000
280 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8560ads-003:eth0:off console=ttyS0,115200"
281 /*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
282 #define CONFIG_BOOTCOMMAND "bootm 0xff400000 0xff700000"
283 #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
285 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
286 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
288 #if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
289 #if defined(CONFIG_PCI)
290 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
291 CFG_CMD_PING | CFG_CMD_I2C) & \
294 #elif defined(CONFIG_TSEC_ENET)
295 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \
298 #elif defined(CONFIG_ETHER_ON_FCC)
299 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
300 CFG_CMD_PING | CFG_CMD_I2C) & \
304 #if defined(CONFIG_PCI)
305 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
306 CFG_CMD_PING | CFG_CMD_I2C)
307 #elif defined(CONFIG_TSEC_ENET)
308 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \
310 #elif defined(CONFIG_ETHER_ON_FCC)
311 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
312 CFG_CMD_PING | CFG_CMD_I2C)
315 #include <cmd_confdefs.h>
317 #undef CONFIG_WATCHDOG /* watchdog disabled */
320 * Miscellaneous configurable options
322 #define CFG_LONGHELP /* undef to save memory */
323 #define CFG_PROMPT "MPC8560ADS=> " /* Monitor Command Prompt */
324 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
325 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
327 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
329 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
330 #define CFG_MAXARGS 16 /* max number of command args */
331 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
332 #define CFG_LOAD_ADDR 0x1000000 /* default load address */
333 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
336 * For booting Linux, the board info and command line data
337 * have to be in the first 8 MB of memory, since this is
338 * the maximum mapped by the Linux kernel during initialization.
340 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
342 /* Cache Configuration */
343 #define CFG_DCACHE_SIZE 32768
344 #define CFG_CACHELINE_SIZE 32
345 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
346 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
350 * Internal Definitions
354 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
355 #define BOOTFLAG_WARM 0x02 /* Software reboot */
357 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
358 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
359 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
362 /*Note: change below for your network setting!!! */
363 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
364 #define CONFIG_ETHADDR 00:01:af:07:9b:8a
365 #define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
366 #define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
369 #define CONFIG_SERVERIP 163.12.64.52
370 #define CONFIG_IPADDR 10.82.0.105
371 #define CONFIG_GATEWAYIP 10.82.1.254
372 #define CONFIG_NETMASK 255.255.254.0
373 #define CONFIG_HOSTNAME MPC8560ADS_PILOT_003
374 #define CONFIG_ROOTPATH /home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
375 #define CONFIG_BOOTFILE pImage
377 #endif /* __CONFIG_H */