2 * Copyright 2004, 2011 Freescale Semiconductor.
3 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 * mpc8560ads board configuration file
12 * Please refer to doc/README.mpc85xx for more info.
14 * Make sure you change the MAC address and other network params first,
15 * search for CONFIG_SERVERIP, etc. in this file.
21 /* High Level Configuration Options */
22 #define CONFIG_BOOKE 1 /* BOOKE */
23 #define CONFIG_E500 1 /* BOOKE e500 family */
24 #define CONFIG_CPM2 1 /* has CPM2 */
27 * default CCARBAR is at 0xff700000
28 * assume U-Boot is less than 0.5MB
30 #define CONFIG_SYS_TEXT_BASE 0xfff80000
32 #define CONFIG_PCI_INDIRECT_BRIDGE
33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
34 #define CONFIG_TSEC_ENET /* tsec ethernet support */
35 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
36 #define CONFIG_ENV_OVERWRITE
37 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
38 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
43 * Two valid values are:
47 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
48 * is likely the desired value here, so that is now the default.
49 * The board, however, can run at 66MHz. In any event, this value
50 * must match the settings of some switches. Details can be found
51 * in the README.mpc85xxads.
54 #ifndef CONFIG_SYS_CLK_FREQ
55 #define CONFIG_SYS_CLK_FREQ 33000000
59 * These can be toggled for performance analysis, otherwise use default.
61 #define CONFIG_L2_CACHE /* toggle L2 cache */
62 #define CONFIG_BTB /* toggle branch predition */
64 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
66 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
67 #define CONFIG_SYS_MEMTEST_END 0x00400000
69 #define CONFIG_SYS_CCSRBAR 0xe0000000
70 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
73 #define CONFIG_SYS_FSL_DDR1
74 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
75 #define CONFIG_DDR_SPD
76 #undef CONFIG_FSL_DDR_INTERACTIVE
78 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
80 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
81 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
83 #define CONFIG_NUM_DDR_CONTROLLERS 1
84 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
85 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
87 /* I2C addresses of SPD EEPROMs */
88 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
90 /* These are used when DDR doesn't use SPD. */
91 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
92 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
93 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
94 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
95 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
96 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
97 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
98 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
101 * SDRAM on the Local Bus
103 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
104 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
106 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
107 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
109 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
110 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
111 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
112 #undef CONFIG_SYS_FLASH_CHECKSUM
113 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
114 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
116 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
118 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
119 #define CONFIG_SYS_RAMBOOT
121 #undef CONFIG_SYS_RAMBOOT
124 #define CONFIG_FLASH_CFI_DRIVER
125 #define CONFIG_SYS_FLASH_CFI
126 #define CONFIG_SYS_FLASH_EMPTY_INFO
128 #undef CONFIG_CLOCKS_IN_MHZ
131 * Local Bus Definitions
135 * Base Register 2 and Option Register 2 configure SDRAM.
136 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
139 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
140 * port-size = 32-bits = BR2[19:20] = 11
141 * no parity checking = BR2[21:22] = 00
142 * SDRAM for MSEL = BR2[24:26] = 011
145 * 0 4 8 12 16 20 24 28
146 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
148 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
149 * FIXME: the top 17 bits of BR2.
152 #define CONFIG_SYS_BR2_PRELIM 0xf0001861
155 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
158 * 64MB mask for AM, OR2[0:7] = 1111 1100
159 * XAM, OR2[17:18] = 11
160 * 9 columns OR2[19-21] = 010
161 * 13 rows OR2[23-25] = 100
162 * EAD set for extra time OR[31] = 1
164 * 0 4 8 12 16 20 24 28
165 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
168 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
170 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
171 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
172 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
173 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
175 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
186 * SDRAM Controller configuration sequence.
188 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
189 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
190 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
191 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
192 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
195 * 32KB, 8-bit wide for ADS config reg
197 #define CONFIG_SYS_BR4_PRELIM 0xf8000801
198 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
199 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
201 #define CONFIG_SYS_INIT_RAM_LOCK 1
202 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
203 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
205 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
206 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
208 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
209 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
212 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
213 #undef CONFIG_CONS_NONE /* define if console on something else */
214 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
216 #define CONFIG_BAUDRATE 115200
218 #define CONFIG_SYS_BAUDRATE_TABLE \
219 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
224 #define CONFIG_SYS_I2C
225 #define CONFIG_SYS_I2C_FSL
226 #define CONFIG_SYS_FSL_I2C_SPEED 400000
227 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
228 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
229 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
232 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
233 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
234 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
235 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
239 * Memory space is mapped 1-1, but I/O space must start from 0.
241 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
242 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
243 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
244 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
245 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
246 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
247 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
248 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
250 #if defined(CONFIG_PCI)
251 #undef CONFIG_EEPRO100
254 #if !defined(CONFIG_PCI_PNP)
255 #define PCI_ENET0_IOADDR 0xe0000000
256 #define PCI_ENET0_MEMADDR 0xe0000000
257 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
260 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
261 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
263 #endif /* CONFIG_PCI */
265 #ifdef CONFIG_TSEC_ENET
268 #define CONFIG_MII 1 /* MII PHY management */
270 #define CONFIG_TSEC1 1
271 #define CONFIG_TSEC1_NAME "TSEC0"
272 #define CONFIG_TSEC2 1
273 #define CONFIG_TSEC2_NAME "TSEC1"
274 #define TSEC1_PHY_ADDR 0
275 #define TSEC2_PHY_ADDR 1
276 #define TSEC1_PHYIDX 0
277 #define TSEC2_PHYIDX 0
278 #define TSEC1_FLAGS TSEC_GIGABIT
279 #define TSEC2_FLAGS TSEC_GIGABIT
281 /* Options are: TSEC[0-1] */
282 #define CONFIG_ETHPRIME "TSEC0"
284 #endif /* CONFIG_TSEC_ENET */
286 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
288 #undef CONFIG_ETHER_NONE /* define if ether on something else */
289 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
291 #if (CONFIG_ETHER_INDEX == 2)
295 * - Select bus for bd/buffers
298 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
299 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
300 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
301 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
302 #define FETH2_RST 0x01
303 #elif (CONFIG_ETHER_INDEX == 3)
304 /* need more definitions here for FE3 */
305 #define FETH3_RST 0x80
306 #endif /* CONFIG_ETHER_INDEX */
309 #define CONFIG_MII 1 /* MII PHY management */
312 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
315 * GPIO pins used for bit-banged MII communications
317 #define MDIO_PORT 2 /* Port C */
318 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
319 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
320 #define MDC_DECLARE MDIO_DECLARE
322 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
323 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
324 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
326 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
327 else iop->pdat &= ~0x00400000
329 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
330 else iop->pdat &= ~0x00200000
332 #define MIIDELAY udelay(1)
339 #ifndef CONFIG_SYS_RAMBOOT
340 #define CONFIG_ENV_IS_IN_FLASH 1
341 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
342 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
343 #define CONFIG_ENV_SIZE 0x2000
345 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
346 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
347 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
348 #define CONFIG_ENV_SIZE 0x2000
351 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
352 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
357 #define CONFIG_BOOTP_BOOTFILESIZE
358 #define CONFIG_BOOTP_BOOTPATH
359 #define CONFIG_BOOTP_GATEWAY
360 #define CONFIG_BOOTP_HOSTNAME
363 * Command line configuration.
365 #define CONFIG_CMD_IRQ
366 #define CONFIG_CMD_REGINFO
368 #if defined(CONFIG_PCI)
369 #define CONFIG_CMD_PCI
372 #if defined(CONFIG_ETHER_ON_FCC)
375 #undef CONFIG_WATCHDOG /* watchdog disabled */
378 * Miscellaneous configurable options
380 #define CONFIG_SYS_LONGHELP /* undef to save memory */
381 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
382 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
383 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
385 #if defined(CONFIG_CMD_KGDB)
386 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
388 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
391 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
392 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
393 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
396 * For booting Linux, the board info and command line data
397 * have to be in the first 64 MB of memory, since this is
398 * the maximum mapped by the Linux kernel during initialization.
400 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
401 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
403 #if defined(CONFIG_CMD_KGDB)
404 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
408 * Environment Configuration
410 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
411 #define CONFIG_HAS_ETH0
412 #define CONFIG_HAS_ETH1
413 #define CONFIG_HAS_ETH2
414 #define CONFIG_HAS_ETH3
417 #define CONFIG_IPADDR 192.168.1.253
419 #define CONFIG_HOSTNAME unknown
420 #define CONFIG_ROOTPATH "/nfsroot"
421 #define CONFIG_BOOTFILE "your.uImage"
423 #define CONFIG_SERVERIP 192.168.1.1
424 #define CONFIG_GATEWAYIP 192.168.1.1
425 #define CONFIG_NETMASK 255.255.255.0
427 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
429 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
431 #define CONFIG_BAUDRATE 115200
433 #define CONFIG_EXTRA_ENV_SETTINGS \
435 "consoledev=ttyCPM\0" \
436 "ramdiskaddr=1000000\0" \
437 "ramdiskfile=your.ramdisk.u-boot\0" \
439 "fdtfile=mpc8560ads.dtb\0"
441 #define CONFIG_NFSBOOTCOMMAND \
442 "setenv bootargs root=/dev/nfs rw " \
443 "nfsroot=$serverip:$rootpath " \
444 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
445 "console=$consoledev,$baudrate $othbootargs;" \
446 "tftp $loadaddr $bootfile;" \
447 "tftp $fdtaddr $fdtfile;" \
448 "bootm $loadaddr - $fdtaddr"
450 #define CONFIG_RAMBOOTCOMMAND \
451 "setenv bootargs root=/dev/ram rw " \
452 "console=$consoledev,$baudrate $othbootargs;" \
453 "tftp $ramdiskaddr $ramdiskfile;" \
454 "tftp $loadaddr $bootfile;" \
455 "tftp $fdtaddr $fdtfile;" \
456 "bootm $loadaddr $ramdiskaddr $fdtaddr"
458 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
460 #endif /* __CONFIG_H */