1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004, 2011 Freescale Semiconductor.
4 * (C) Copyright 2002,2003 Motorola,Inc.
5 * Xianghua Xiao <X.Xiao@motorola.com>
9 * mpc8560ads board configuration file
11 * Please refer to doc/README.mpc85xx for more info.
13 * Make sure you change the MAC address and other network params first,
14 * search for CONFIG_SERVERIP, etc. in this file.
20 #include <linux/delay.h>
22 /* High Level Configuration Options */
23 #define CONFIG_CPM2 1 /* has CPM2 */
26 * default CCARBAR is at 0xff700000
27 * assume U-Boot is less than 0.5MB
30 #define CONFIG_PCI_INDIRECT_BRIDGE
31 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
32 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
33 #define CONFIG_ENV_OVERWRITE
34 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
39 * Two valid values are:
43 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
44 * is likely the desired value here, so that is now the default.
45 * The board, however, can run at 66MHz. In any event, this value
46 * must match the settings of some switches. Details can be found
47 * in the README.mpc85xxads.
50 #ifndef CONFIG_SYS_CLK_FREQ
51 #define CONFIG_SYS_CLK_FREQ 33000000
55 * These can be toggled for performance analysis, otherwise use default.
57 #define CONFIG_L2_CACHE /* toggle L2 cache */
58 #define CONFIG_BTB /* toggle branch predition */
60 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
62 #define CONFIG_SYS_CCSRBAR 0xe0000000
63 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
66 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
67 #define CONFIG_DDR_SPD
69 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
71 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
72 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
74 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
75 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
77 /* I2C addresses of SPD EEPROMs */
78 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
80 /* These are used when DDR doesn't use SPD. */
81 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
82 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
83 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
84 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
85 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
86 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
87 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
88 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
91 * SDRAM on the Local Bus
93 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
94 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
96 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
97 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
99 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
100 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
101 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
102 #undef CONFIG_SYS_FLASH_CHECKSUM
103 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
104 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
106 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
108 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
109 #define CONFIG_SYS_RAMBOOT
111 #undef CONFIG_SYS_RAMBOOT
114 #define CONFIG_SYS_FLASH_EMPTY_INFO
116 #undef CONFIG_CLOCKS_IN_MHZ
119 * Local Bus Definitions
123 * Base Register 2 and Option Register 2 configure SDRAM.
124 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
127 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
128 * port-size = 32-bits = BR2[19:20] = 11
129 * no parity checking = BR2[21:22] = 00
130 * SDRAM for MSEL = BR2[24:26] = 011
133 * 0 4 8 12 16 20 24 28
134 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
136 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
137 * FIXME: the top 17 bits of BR2.
140 #define CONFIG_SYS_BR2_PRELIM 0xf0001861
143 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
146 * 64MB mask for AM, OR2[0:7] = 1111 1100
147 * XAM, OR2[17:18] = 11
148 * 9 columns OR2[19-21] = 010
149 * 13 rows OR2[23-25] = 100
150 * EAD set for extra time OR[31] = 1
152 * 0 4 8 12 16 20 24 28
153 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
156 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
158 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
159 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
160 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
161 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
163 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
174 * SDRAM Controller configuration sequence.
176 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
177 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
178 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
179 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
180 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
183 * 32KB, 8-bit wide for ADS config reg
185 #define CONFIG_SYS_BR4_PRELIM 0xf8000801
186 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
187 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
189 #define CONFIG_SYS_INIT_RAM_LOCK 1
190 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
191 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
193 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
194 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
196 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
197 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
200 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
201 #undef CONFIG_CONS_NONE /* define if console on something else */
203 #define CONFIG_SYS_BAUDRATE_TABLE \
204 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
209 #define CONFIG_SYS_I2C
210 #define CONFIG_SYS_I2C_FSL
211 #define CONFIG_SYS_FSL_I2C_SPEED 400000
212 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
213 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
214 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
217 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
218 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
219 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
220 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
224 * Memory space is mapped 1-1, but I/O space must start from 0.
226 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
227 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
228 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
229 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
230 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
231 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
232 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
233 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
235 #if defined(CONFIG_PCI)
236 #undef CONFIG_EEPRO100
239 #if !defined(CONFIG_PCI_PNP)
240 #define PCI_ENET0_IOADDR 0xe0000000
241 #define PCI_ENET0_MEMADDR 0xe0000000
242 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
245 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
246 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
248 #endif /* CONFIG_PCI */
250 #ifdef CONFIG_TSEC_ENET
252 #define CONFIG_TSEC1 1
253 #define CONFIG_TSEC1_NAME "TSEC0"
254 #define CONFIG_TSEC2 1
255 #define CONFIG_TSEC2_NAME "TSEC1"
256 #define TSEC1_PHY_ADDR 0
257 #define TSEC2_PHY_ADDR 1
258 #define TSEC1_PHYIDX 0
259 #define TSEC2_PHYIDX 0
260 #define TSEC1_FLAGS TSEC_GIGABIT
261 #define TSEC2_FLAGS TSEC_GIGABIT
263 /* Options are: TSEC[0-1] */
264 #define CONFIG_ETHPRIME "TSEC0"
266 #endif /* CONFIG_TSEC_ENET */
268 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
270 #undef CONFIG_ETHER_NONE /* define if ether on something else */
271 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
273 #if (CONFIG_ETHER_INDEX == 2)
277 * - Select bus for bd/buffers
280 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
281 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
282 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
283 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
284 #define FETH2_RST 0x01
285 #elif (CONFIG_ETHER_INDEX == 3)
286 /* need more definitions here for FE3 */
287 #define FETH3_RST 0x80
288 #endif /* CONFIG_ETHER_INDEX */
291 * GPIO pins used for bit-banged MII communications
293 #define MDIO_PORT 2 /* Port C */
294 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
295 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
296 #define MDC_DECLARE MDIO_DECLARE
298 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
299 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
300 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
302 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
303 else iop->pdat &= ~0x00400000
305 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
306 else iop->pdat &= ~0x00200000
308 #define MIIDELAY udelay(1)
316 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
317 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
322 #define CONFIG_BOOTP_BOOTFILESIZE
324 #undef CONFIG_WATCHDOG /* watchdog disabled */
327 * Miscellaneous configurable options
329 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
331 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
334 * For booting Linux, the board info and command line data
335 * have to be in the first 64 MB of memory, since this is
336 * the maximum mapped by the Linux kernel during initialization.
338 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
339 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
341 #if defined(CONFIG_CMD_KGDB)
342 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
346 * Environment Configuration
348 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
349 #define CONFIG_HAS_ETH0
350 #define CONFIG_HAS_ETH1
351 #define CONFIG_HAS_ETH2
352 #define CONFIG_HAS_ETH3
355 #define CONFIG_IPADDR 192.168.1.253
357 #define CONFIG_HOSTNAME "unknown"
358 #define CONFIG_ROOTPATH "/nfsroot"
359 #define CONFIG_BOOTFILE "your.uImage"
361 #define CONFIG_SERVERIP 192.168.1.1
362 #define CONFIG_GATEWAYIP 192.168.1.1
363 #define CONFIG_NETMASK 255.255.255.0
365 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
367 #define CONFIG_EXTRA_ENV_SETTINGS \
369 "consoledev=ttyCPM\0" \
370 "ramdiskaddr=1000000\0" \
371 "ramdiskfile=your.ramdisk.u-boot\0" \
373 "fdtfile=mpc8560ads.dtb\0"
375 #define CONFIG_NFSBOOTCOMMAND \
376 "setenv bootargs root=/dev/nfs rw " \
377 "nfsroot=$serverip:$rootpath " \
378 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
379 "console=$consoledev,$baudrate $othbootargs;" \
380 "tftp $loadaddr $bootfile;" \
381 "tftp $fdtaddr $fdtfile;" \
382 "bootm $loadaddr - $fdtaddr"
384 #define CONFIG_RAMBOOTCOMMAND \
385 "setenv bootargs root=/dev/ram rw " \
386 "console=$consoledev,$baudrate $othbootargs;" \
387 "tftp $ramdiskaddr $ramdiskfile;" \
388 "tftp $loadaddr $bootfile;" \
389 "tftp $fdtaddr $fdtfile;" \
390 "bootm $loadaddr $ramdiskaddr $fdtaddr"
392 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
394 #endif /* __CONFIG_H */