1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004, 2011 Freescale Semiconductor.
7 * mpc8555cds board configuration file
9 * Please refer to doc/README.mpc85xxcds for more info.
15 /* High Level Configuration Options */
16 #define CONFIG_CPM2 1 /* has CPM2 */
18 #define CONFIG_PCI_INDIRECT_BRIDGE
19 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
21 #define CONFIG_FSL_VIA
24 extern unsigned long get_clock_freq(void);
26 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
29 * These can be toggled for performance analysis, otherwise use default.
31 #define CONFIG_L2_CACHE /* toggle L2 cache */
32 #define CONFIG_BTB /* toggle branch predition */
34 #define CONFIG_SYS_CCSRBAR 0xe0000000
35 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
38 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
39 #define CONFIG_DDR_SPD
41 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
43 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
44 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
46 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
47 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
49 /* I2C addresses of SPD EEPROMs */
50 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
52 /* Make sure required options are set */
53 #ifndef CONFIG_SPD_EEPROM
54 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
58 * Local Bus Definitions
62 * FLASH on the Local Bus
63 * Two banks, 8M each, using the CFI driver.
64 * Boot from BR0/OR0 bank at 0xff00_0000
65 * Alternate BR1/OR1 bank at 0xff80_0000
68 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
69 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
70 * Port Size = 16 bits = BRx[19:20] = 10
71 * Use GPCM = BRx[24:26] = 000
74 * 0 4 8 12 16 20 24 28
75 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
76 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
79 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
80 * Reserved ORx[17:18] = 11, confusion here?
82 * ACS = half cycle delay = ORx[21:22] = 11
83 * SCY = 6 = ORx[24:27] = 0110
84 * TRLX = use relaxed timing = ORx[29] = 1
85 * EAD = use external address latch delay = OR[31] = 1
87 * 0 4 8 12 16 20 24 28
88 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
91 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
93 #define CONFIG_SYS_BR0_PRELIM 0xff801001
94 #define CONFIG_SYS_BR1_PRELIM 0xff001001
96 #define CONFIG_SYS_OR0_PRELIM 0xff806e65
97 #define CONFIG_SYS_OR1_PRELIM 0xff806e65
99 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
100 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
101 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
102 #undef CONFIG_SYS_FLASH_CHECKSUM
103 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
104 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
106 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
108 #define CONFIG_SYS_FLASH_EMPTY_INFO
111 * SDRAM on the Local Bus
113 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
114 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
117 * Base Register 2 and Option Register 2 configure SDRAM.
118 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
121 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
122 * port-size = 32-bits = BR2[19:20] = 11
123 * no parity checking = BR2[21:22] = 00
124 * SDRAM for MSEL = BR2[24:26] = 011
127 * 0 4 8 12 16 20 24 28
128 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
130 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
131 * FIXME: the top 17 bits of BR2.
134 #define CONFIG_SYS_BR2_PRELIM 0xf0001861
137 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
140 * 64MB mask for AM, OR2[0:7] = 1111 1100
141 * XAM, OR2[17:18] = 11
142 * 9 columns OR2[19-21] = 010
143 * 13 rows OR2[23-25] = 100
144 * EAD set for extra time OR[31] = 1
146 * 0 4 8 12 16 20 24 28
147 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
150 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
152 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
153 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
154 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
155 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
158 * Common settings for all Local Bus SDRAM commands.
159 * At run time, either BSMA1516 (for CPU 1.1)
160 * or BSMA1617 (for CPU 1.0) (old)
163 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
173 * The CADMUS registers are connected to CS3 on CDS.
174 * The new memory map places CADMUS at 0xf8000000.
177 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
178 * port-size = 8-bits = BR[19:20] = 01
179 * no parity checking = BR[21:22] = 00
180 * GPMC for MSEL = BR[24:26] = 000
183 * 0 4 8 12 16 20 24 28
184 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
187 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
188 * disable buffer ctrl OR[19] = 0
192 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
196 * EAD extra time OR[31] = 1
198 * 0 4 8 12 16 20 24 28
199 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
202 #define CONFIG_FSL_CADMUS
204 #define CADMUS_BASE_ADDR 0xf8000000
205 #define CONFIG_SYS_BR3_PRELIM 0xf8000801
206 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
208 #define CONFIG_SYS_INIT_RAM_LOCK 1
209 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
210 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
212 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
213 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
215 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
216 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
219 #define CONFIG_SYS_NS16550_SERIAL
220 #define CONFIG_SYS_NS16550_REG_SIZE 1
221 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
223 #define CONFIG_SYS_BAUDRATE_TABLE \
224 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
226 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
227 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
232 #define CONFIG_SYS_I2C
233 #define CONFIG_SYS_I2C_FSL
234 #define CONFIG_SYS_FSL_I2C_SPEED 400000
235 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
236 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
237 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
240 #define CONFIG_ID_EEPROM
241 #define CONFIG_SYS_I2C_EEPROM_CCID
242 #define CONFIG_SYS_ID_EEPROM
243 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
244 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
248 * Addresses are mapped 1-1.
250 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
251 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
252 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
253 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
254 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
255 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
256 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
257 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
259 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
260 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
261 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
262 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
263 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
264 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000
265 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
266 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
276 #if defined(CONFIG_PCI)
278 #define CONFIG_MPC85XX_PCI2
281 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
282 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
284 #endif /* CONFIG_PCI */
286 #if defined(CONFIG_TSEC_ENET)
288 #define CONFIG_TSEC1 1
289 #define CONFIG_TSEC1_NAME "TSEC0"
290 #define CONFIG_TSEC2 1
291 #define CONFIG_TSEC2_NAME "TSEC1"
292 #define TSEC1_PHY_ADDR 0
293 #define TSEC2_PHY_ADDR 1
294 #define TSEC1_PHYIDX 0
295 #define TSEC2_PHYIDX 0
296 #define TSEC1_FLAGS TSEC_GIGABIT
297 #define TSEC2_FLAGS TSEC_GIGABIT
299 /* Options are: TSEC[0-1] */
300 #define CONFIG_ETHPRIME "TSEC0"
302 #endif /* CONFIG_TSEC_ENET */
308 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
309 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
314 #define CONFIG_BOOTP_BOOTFILESIZE
316 #undef CONFIG_WATCHDOG /* watchdog disabled */
319 * Miscellaneous configurable options
321 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
324 * For booting Linux, the board info and command line data
325 * have to be in the first 64 MB of memory, since this is
326 * the maximum mapped by the Linux kernel during initialization.
328 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
329 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
331 #if defined(CONFIG_CMD_KGDB)
332 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
336 * Environment Configuration
338 #if defined(CONFIG_TSEC_ENET)
339 #define CONFIG_HAS_ETH0
340 #define CONFIG_HAS_ETH1
341 #define CONFIG_HAS_ETH2
344 #define CONFIG_IPADDR 192.168.1.253
346 #define CONFIG_HOSTNAME "unknown"
347 #define CONFIG_ROOTPATH "/nfsroot"
348 #define CONFIG_BOOTFILE "your.uImage"
350 #define CONFIG_SERVERIP 192.168.1.1
351 #define CONFIG_GATEWAYIP 192.168.1.1
352 #define CONFIG_NETMASK 255.255.255.0
354 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
356 #define CONFIG_EXTRA_ENV_SETTINGS \
358 "consoledev=ttyS1\0" \
359 "ramdiskaddr=600000\0" \
360 "ramdiskfile=your.ramdisk.u-boot\0" \
362 "fdtfile=your.fdt.dtb\0"
364 #define CONFIG_NFSBOOTCOMMAND \
365 "setenv bootargs root=/dev/nfs rw " \
366 "nfsroot=$serverip:$rootpath " \
367 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
368 "console=$consoledev,$baudrate $othbootargs;" \
369 "tftp $loadaddr $bootfile;" \
370 "tftp $fdtaddr $fdtfile;" \
371 "bootm $loadaddr - $fdtaddr"
373 #define CONFIG_RAMBOOTCOMMAND \
374 "setenv bootargs root=/dev/ram rw " \
375 "console=$consoledev,$baudrate $othbootargs;" \
376 "tftp $ramdiskaddr $ramdiskfile;" \
377 "tftp $loadaddr $bootfile;" \
378 "bootm $loadaddr $ramdiskaddr"
380 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
382 #endif /* __CONFIG_H */