1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
8 * mpc8548cds board configuration file
10 * Please refer to doc/README.mpc85xxcds for more info.
16 #define CONFIG_SYS_SRIO
17 #define CONFIG_SRIO1 /* SRIO port 1 */
19 #define CONFIG_PCI1 /* PCI controller 1 */
20 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
23 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
26 #include <linux/stringify.h>
27 extern unsigned long get_board_sys_clk(void);
29 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
32 * These can be toggled for performance analysis, otherwise use default.
34 #define CONFIG_L2_CACHE /* toggle L2 cache */
35 #define CONFIG_BTB /* toggle branch predition */
38 * Only possible on E500 Version 2 or newer cores.
40 #define CONFIG_ENABLE_36BIT_PHYS 1
42 #define CONFIG_SYS_CCSRBAR 0xe0000000
43 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
46 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
48 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
50 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
51 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
53 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
54 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
56 /* I2C addresses of SPD EEPROMs */
57 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
59 /* Make sure required options are set */
60 #ifndef CONFIG_SPD_EEPROM
61 #error ("CONFIG_SPD_EEPROM is required")
65 * Physical Address Map
68 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
69 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
70 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
71 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
72 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
73 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
74 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
75 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
76 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
77 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
78 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
81 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable
82 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
83 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
84 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
85 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
86 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
87 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
88 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
89 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
90 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
91 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
96 * Local Bus Definitions
100 * FLASH on the Local Bus
101 * Two banks, 8M each, using the CFI driver.
102 * Boot from BR0/OR0 bank at 0xff00_0000
103 * Alternate BR1/OR1 bank at 0xff80_0000
106 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
107 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
108 * Port Size = 16 bits = BRx[19:20] = 10
109 * Use GPCM = BRx[24:26] = 000
110 * Valid = BRx[31] = 1
112 * 0 4 8 12 16 20 24 28
113 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
114 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
117 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
118 * Reserved ORx[17:18] = 11, confusion here?
120 * ACS = half cycle delay = ORx[21:22] = 11
121 * SCY = 6 = ORx[24:27] = 0110
122 * TRLX = use relaxed timing = ORx[29] = 1
123 * EAD = use external address latch delay = OR[31] = 1
125 * 0 4 8 12 16 20 24 28
126 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
129 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
130 #ifdef CONFIG_PHYS_64BIT
131 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
133 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
136 #define CONFIG_SYS_FLASH_BANKS_LIST \
137 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
138 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
139 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
140 #undef CONFIG_SYS_FLASH_CHECKSUM
141 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
142 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
144 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
146 #define CONFIG_SYS_FLASH_EMPTY_INFO
148 #define CONFIG_HWCONFIG /* enable hwconfig */
151 * SDRAM on the Local Bus
153 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
154 #ifdef CONFIG_PHYS_64BIT
155 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
157 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
159 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
162 * Base Register 2 and Option Register 2 configure SDRAM.
163 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
166 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
167 * port-size = 32-bits = BR2[19:20] = 11
168 * no parity checking = BR2[21:22] = 00
169 * SDRAM for MSEL = BR2[24:26] = 011
172 * 0 4 8 12 16 20 24 28
173 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
175 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
176 * FIXME: the top 17 bits of BR2.
180 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
183 * 64MB mask for AM, OR2[0:7] = 1111 1100
184 * XAM, OR2[17:18] = 11
185 * 9 columns OR2[19-21] = 010
186 * 13 rows OR2[23-25] = 100
187 * EAD set for extra time OR[31] = 1
189 * 0 4 8 12 16 20 24 28
190 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
193 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
194 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
195 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
196 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
199 * Common settings for all Local Bus SDRAM commands.
200 * At run time, either BSMA1516 (for CPU 1.1)
201 * or BSMA1617 (for CPU 1.0) (old)
204 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
214 * The CADMUS registers are connected to CS3 on CDS.
215 * The new memory map places CADMUS at 0xf8000000.
218 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
219 * port-size = 8-bits = BR[19:20] = 01
220 * no parity checking = BR[21:22] = 00
221 * GPMC for MSEL = BR[24:26] = 000
224 * 0 4 8 12 16 20 24 28
225 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
228 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
229 * disable buffer ctrl OR[19] = 0
233 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
237 * EAD extra time OR[31] = 1
239 * 0 4 8 12 16 20 24 28
240 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
243 #define CONFIG_FSL_CADMUS
245 #define CADMUS_BASE_ADDR 0xf8000000
246 #ifdef CONFIG_PHYS_64BIT
247 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
249 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
252 #define CONFIG_SYS_INIT_RAM_LOCK 1
253 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
254 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
256 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
257 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
259 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
262 #define CONFIG_SYS_NS16550_SERIAL
263 #define CONFIG_SYS_NS16550_REG_SIZE 1
264 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
266 #define CONFIG_SYS_BAUDRATE_TABLE \
267 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
269 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
270 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
275 #if !CONFIG_IS_ENABLED(DM_I2C)
276 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
278 #define CONFIG_SYS_SPD_BUS_NUM 0
282 #define CONFIG_SYS_I2C_EEPROM_CCID
286 * Memory space is mapped 1-1, but I/O space must start from 0.
288 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
289 #ifdef CONFIG_PHYS_64BIT
290 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
291 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
293 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
294 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
296 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
297 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
298 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
299 #ifdef CONFIG_PHYS_64BIT
300 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
302 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
304 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
307 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
308 #ifdef CONFIG_PHYS_64BIT
309 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
311 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
313 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
314 #ifdef CONFIG_PHYS_64BIT
315 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
317 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
324 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
325 #ifdef CONFIG_PHYS_64BIT
326 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
328 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
330 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
340 #if defined(CONFIG_PCI)
341 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
342 #endif /* CONFIG_PCI */
344 #if defined(CONFIG_TSEC_ENET)
346 #define CONFIG_TSEC1 1
347 #define CONFIG_TSEC1_NAME "eTSEC0"
348 #define CONFIG_TSEC2 1
349 #define CONFIG_TSEC2_NAME "eTSEC1"
350 #define CONFIG_TSEC3 1
351 #define CONFIG_TSEC3_NAME "eTSEC2"
353 #define CONFIG_TSEC4_NAME "eTSEC3"
354 #undef CONFIG_MPC85XX_FEC
356 #define TSEC1_PHY_ADDR 0
357 #define TSEC2_PHY_ADDR 1
358 #define TSEC3_PHY_ADDR 2
359 #define TSEC4_PHY_ADDR 3
361 #define TSEC1_PHYIDX 0
362 #define TSEC2_PHYIDX 0
363 #define TSEC3_PHYIDX 0
364 #define TSEC4_PHYIDX 0
365 #define TSEC1_FLAGS TSEC_GIGABIT
366 #define TSEC2_FLAGS TSEC_GIGABIT
367 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
368 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
370 /* Options are: eTSEC[0-3] */
371 #define CONFIG_ETHPRIME "eTSEC0"
372 #endif /* CONFIG_TSEC_ENET */
378 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
379 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
384 #define CONFIG_BOOTP_BOOTFILESIZE
387 * Miscellaneous configurable options
391 * For booting Linux, the board info and command line data
392 * have to be in the first 64 MB of memory, since this is
393 * the maximum mapped by the Linux kernel during initialization.
395 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
396 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
399 * Environment Configuration
401 #if defined(CONFIG_TSEC_ENET)
402 #define CONFIG_HAS_ETH0
403 #define CONFIG_HAS_ETH1
404 #define CONFIG_HAS_ETH2
405 #define CONFIG_HAS_ETH3
408 #define CONFIG_IPADDR 192.168.1.253
410 #define CONFIG_HOSTNAME "unknown"
411 #define CONFIG_ROOTPATH "/nfsroot"
412 #define CONFIG_BOOTFILE "8548cds/uImage.uboot"
413 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
415 #define CONFIG_SERVERIP 192.168.1.1
416 #define CONFIG_GATEWAYIP 192.168.1.1
417 #define CONFIG_NETMASK 255.255.255.0
419 #define CONFIG_EXTRA_ENV_SETTINGS \
420 "hwconfig=fsl_ddr:ecc=off\0" \
422 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
423 "tftpflash=tftpboot $loadaddr $uboot; " \
424 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
426 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
428 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
430 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
432 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
434 "consoledev=ttyS1\0" \
435 "ramdiskaddr=2000000\0" \
436 "ramdiskfile=ramdisk.uboot\0" \
437 "fdtaddr=1e00000\0" \
438 "fdtfile=mpc8548cds.dtb\0"
440 #endif /* __CONFIG_H */