2 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
4 * SPDX-License-Identifier: GPL-2.0+
8 * mpc8548cds board configuration file
10 * Please refer to doc/README.mpc85xxcds for more info.
16 #ifndef CONFIG_SYS_TEXT_BASE
17 #define CONFIG_SYS_TEXT_BASE 0xfff80000
20 #define CONFIG_SYS_SRIO
21 #define CONFIG_SRIO1 /* SRIO port 1 */
23 #define CONFIG_PCI1 /* PCI controller 1 */
24 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
26 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
27 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
28 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
29 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
31 #define CONFIG_TSEC_ENET /* tsec ethernet support */
32 #define CONFIG_ENV_OVERWRITE
33 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
35 #define CONFIG_FSL_VIA
38 extern unsigned long get_clock_freq(void);
40 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
43 * These can be toggled for performance analysis, otherwise use default.
45 #define CONFIG_L2_CACHE /* toggle L2 cache */
46 #define CONFIG_BTB /* toggle branch predition */
49 * Only possible on E500 Version 2 or newer cores.
51 #define CONFIG_ENABLE_36BIT_PHYS 1
53 #ifdef CONFIG_PHYS_64BIT
54 #define CONFIG_ADDR_MAP
55 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
58 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
59 #define CONFIG_SYS_MEMTEST_END 0x00400000
61 #define CONFIG_SYS_CCSRBAR 0xe0000000
62 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
65 #undef CONFIG_FSL_DDR_INTERACTIVE
66 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
67 #define CONFIG_DDR_SPD
69 #define CONFIG_DDR_ECC
70 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
71 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
73 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
74 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
76 #define CONFIG_NUM_DDR_CONTROLLERS 1
77 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
78 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
80 /* I2C addresses of SPD EEPROMs */
81 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
83 /* Make sure required options are set */
84 #ifndef CONFIG_SPD_EEPROM
85 #error ("CONFIG_SPD_EEPROM is required")
88 #undef CONFIG_CLOCKS_IN_MHZ
90 * Physical Address Map
93 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
94 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
95 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
96 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
97 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
98 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
99 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
100 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
101 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
102 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
103 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
106 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable
107 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
108 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
109 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
110 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
111 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
112 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
113 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
114 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
115 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
116 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
121 * Local Bus Definitions
125 * FLASH on the Local Bus
126 * Two banks, 8M each, using the CFI driver.
127 * Boot from BR0/OR0 bank at 0xff00_0000
128 * Alternate BR1/OR1 bank at 0xff80_0000
131 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
132 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
133 * Port Size = 16 bits = BRx[19:20] = 10
134 * Use GPCM = BRx[24:26] = 000
135 * Valid = BRx[31] = 1
137 * 0 4 8 12 16 20 24 28
138 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
139 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
142 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
143 * Reserved ORx[17:18] = 11, confusion here?
145 * ACS = half cycle delay = ORx[21:22] = 11
146 * SCY = 6 = ORx[24:27] = 0110
147 * TRLX = use relaxed timing = ORx[29] = 1
148 * EAD = use external address latch delay = OR[31] = 1
150 * 0 4 8 12 16 20 24 28
151 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
154 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
155 #ifdef CONFIG_PHYS_64BIT
156 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
158 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
161 #define CONFIG_SYS_BR0_PRELIM \
162 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
163 #define CONFIG_SYS_BR1_PRELIM \
164 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
166 #define CONFIG_SYS_OR0_PRELIM 0xff806e65
167 #define CONFIG_SYS_OR1_PRELIM 0xff806e65
169 #define CONFIG_SYS_FLASH_BANKS_LIST \
170 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
171 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
172 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
173 #undef CONFIG_SYS_FLASH_CHECKSUM
174 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
175 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
177 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
179 #define CONFIG_FLASH_CFI_DRIVER
180 #define CONFIG_SYS_FLASH_CFI
181 #define CONFIG_SYS_FLASH_EMPTY_INFO
183 #define CONFIG_HWCONFIG /* enable hwconfig */
186 * SDRAM on the Local Bus
188 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
189 #ifdef CONFIG_PHYS_64BIT
190 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
192 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
194 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
197 * Base Register 2 and Option Register 2 configure SDRAM.
198 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
201 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
202 * port-size = 32-bits = BR2[19:20] = 11
203 * no parity checking = BR2[21:22] = 00
204 * SDRAM for MSEL = BR2[24:26] = 011
207 * 0 4 8 12 16 20 24 28
208 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
210 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
211 * FIXME: the top 17 bits of BR2.
214 #define CONFIG_SYS_BR2_PRELIM \
215 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
216 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
219 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
222 * 64MB mask for AM, OR2[0:7] = 1111 1100
223 * XAM, OR2[17:18] = 11
224 * 9 columns OR2[19-21] = 010
225 * 13 rows OR2[23-25] = 100
226 * EAD set for extra time OR[31] = 1
228 * 0 4 8 12 16 20 24 28
229 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
232 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
234 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
235 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
236 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
237 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
240 * Common settings for all Local Bus SDRAM commands.
241 * At run time, either BSMA1516 (for CPU 1.1)
242 * or BSMA1617 (for CPU 1.0) (old)
245 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
255 * The CADMUS registers are connected to CS3 on CDS.
256 * The new memory map places CADMUS at 0xf8000000.
259 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
260 * port-size = 8-bits = BR[19:20] = 01
261 * no parity checking = BR[21:22] = 00
262 * GPMC for MSEL = BR[24:26] = 000
265 * 0 4 8 12 16 20 24 28
266 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
269 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
270 * disable buffer ctrl OR[19] = 0
274 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
278 * EAD extra time OR[31] = 1
280 * 0 4 8 12 16 20 24 28
281 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
284 #define CONFIG_FSL_CADMUS
286 #define CADMUS_BASE_ADDR 0xf8000000
287 #ifdef CONFIG_PHYS_64BIT
288 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
290 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
292 #define CONFIG_SYS_BR3_PRELIM \
293 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
294 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
296 #define CONFIG_SYS_INIT_RAM_LOCK 1
297 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
298 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
300 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
301 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
303 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
304 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
307 #define CONFIG_CONS_INDEX 2
308 #define CONFIG_SYS_NS16550_SERIAL
309 #define CONFIG_SYS_NS16550_REG_SIZE 1
310 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
312 #define CONFIG_SYS_BAUDRATE_TABLE \
313 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
315 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
316 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
321 #define CONFIG_SYS_I2C
322 #define CONFIG_SYS_I2C_FSL
323 #define CONFIG_SYS_FSL_I2C_SPEED 400000
324 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
325 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
326 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
329 #define CONFIG_ID_EEPROM
330 #define CONFIG_SYS_I2C_EEPROM_CCID
331 #define CONFIG_SYS_ID_EEPROM
332 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
333 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
337 * Memory space is mapped 1-1, but I/O space must start from 0.
339 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
340 #ifdef CONFIG_PHYS_64BIT
341 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
342 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
344 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
345 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
347 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
348 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
349 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
350 #ifdef CONFIG_PHYS_64BIT
351 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
353 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
355 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
358 #define CONFIG_SYS_PCIE1_NAME "Slot"
359 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
360 #ifdef CONFIG_PHYS_64BIT
361 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
362 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
364 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
365 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
367 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
368 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
369 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
370 #ifdef CONFIG_PHYS_64BIT
371 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
373 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
375 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
381 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
382 #ifdef CONFIG_PHYS_64BIT
383 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
385 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
387 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
397 #if defined(CONFIG_PCI)
398 #undef CONFIG_EEPRO100
401 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
403 #endif /* CONFIG_PCI */
405 #if defined(CONFIG_TSEC_ENET)
407 #define CONFIG_MII 1 /* MII PHY management */
408 #define CONFIG_TSEC1 1
409 #define CONFIG_TSEC1_NAME "eTSEC0"
410 #define CONFIG_TSEC2 1
411 #define CONFIG_TSEC2_NAME "eTSEC1"
412 #define CONFIG_TSEC3 1
413 #define CONFIG_TSEC3_NAME "eTSEC2"
415 #define CONFIG_TSEC4_NAME "eTSEC3"
416 #undef CONFIG_MPC85XX_FEC
418 #define CONFIG_PHY_MARVELL
420 #define TSEC1_PHY_ADDR 0
421 #define TSEC2_PHY_ADDR 1
422 #define TSEC3_PHY_ADDR 2
423 #define TSEC4_PHY_ADDR 3
425 #define TSEC1_PHYIDX 0
426 #define TSEC2_PHYIDX 0
427 #define TSEC3_PHYIDX 0
428 #define TSEC4_PHYIDX 0
429 #define TSEC1_FLAGS TSEC_GIGABIT
430 #define TSEC2_FLAGS TSEC_GIGABIT
431 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
432 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
434 /* Options are: eTSEC[0-3] */
435 #define CONFIG_ETHPRIME "eTSEC0"
436 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
437 #endif /* CONFIG_TSEC_ENET */
442 #define CONFIG_ENV_IS_IN_FLASH 1
443 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
444 #define CONFIG_ENV_ADDR 0xfff80000
446 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
448 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */
449 #define CONFIG_ENV_SIZE 0x2000
451 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
452 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
457 #define CONFIG_BOOTP_BOOTFILESIZE
458 #define CONFIG_BOOTP_BOOTPATH
459 #define CONFIG_BOOTP_GATEWAY
460 #define CONFIG_BOOTP_HOSTNAME
463 * Command line configuration.
465 #define CONFIG_CMD_IRQ
466 #define CONFIG_CMD_REGINFO
468 #if defined(CONFIG_PCI)
469 #define CONFIG_CMD_PCI
472 #undef CONFIG_WATCHDOG /* watchdog disabled */
475 * Miscellaneous configurable options
477 #define CONFIG_SYS_LONGHELP /* undef to save memory */
478 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
479 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
480 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
481 #if defined(CONFIG_CMD_KGDB)
482 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
484 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
486 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
487 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
488 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
491 * For booting Linux, the board info and command line data
492 * have to be in the first 64 MB of memory, since this is
493 * the maximum mapped by the Linux kernel during initialization.
495 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
496 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
498 #if defined(CONFIG_CMD_KGDB)
499 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
503 * Environment Configuration
505 #if defined(CONFIG_TSEC_ENET)
506 #define CONFIG_HAS_ETH0
507 #define CONFIG_HAS_ETH1
508 #define CONFIG_HAS_ETH2
509 #define CONFIG_HAS_ETH3
512 #define CONFIG_IPADDR 192.168.1.253
514 #define CONFIG_HOSTNAME unknown
515 #define CONFIG_ROOTPATH "/nfsroot"
516 #define CONFIG_BOOTFILE "8548cds/uImage.uboot"
517 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
519 #define CONFIG_SERVERIP 192.168.1.1
520 #define CONFIG_GATEWAYIP 192.168.1.1
521 #define CONFIG_NETMASK 255.255.255.0
523 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
525 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
527 #define CONFIG_BAUDRATE 115200
529 #define CONFIG_EXTRA_ENV_SETTINGS \
530 "hwconfig=fsl_ddr:ecc=off\0" \
532 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
533 "tftpflash=tftpboot $loadaddr $uboot; " \
534 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
536 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
538 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
540 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
542 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
544 "consoledev=ttyS1\0" \
545 "ramdiskaddr=2000000\0" \
546 "ramdiskfile=ramdisk.uboot\0" \
547 "fdtaddr=1e00000\0" \
548 "fdtfile=mpc8548cds.dtb\0"
550 #define CONFIG_NFSBOOTCOMMAND \
551 "setenv bootargs root=/dev/nfs rw " \
552 "nfsroot=$serverip:$rootpath " \
553 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
554 "console=$consoledev,$baudrate $othbootargs;" \
555 "tftp $loadaddr $bootfile;" \
556 "tftp $fdtaddr $fdtfile;" \
557 "bootm $loadaddr - $fdtaddr"
559 #define CONFIG_RAMBOOTCOMMAND \
560 "setenv bootargs root=/dev/ram rw " \
561 "console=$consoledev,$baudrate $othbootargs;" \
562 "tftp $ramdiskaddr $ramdiskfile;" \
563 "tftp $loadaddr $bootfile;" \
564 "tftp $fdtaddr $fdtfile;" \
565 "bootm $loadaddr $ramdiskaddr $fdtaddr"
567 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
569 #endif /* __CONFIG_H */