1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
8 * mpc8548cds board configuration file
10 * Please refer to doc/README.mpc85xxcds for more info.
16 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
19 #include <linux/stringify.h>
23 * These can be toggled for performance analysis, otherwise use default.
25 #define CONFIG_L2_CACHE /* toggle L2 cache */
28 * Only possible on E500 Version 2 or newer cores.
31 #define CFG_SYS_CCSRBAR 0xe0000000
32 #define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
35 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
37 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
39 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
40 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
42 /* I2C addresses of SPD EEPROMs */
43 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
45 /* Make sure required options are set */
46 #ifndef CONFIG_SPD_EEPROM
47 #error ("CONFIG_SPD_EEPROM is required")
51 * Physical Address Map
54 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
55 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
56 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
57 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
58 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
59 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
60 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
61 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
62 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
63 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
64 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
67 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable
68 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
69 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
70 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
71 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
72 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
73 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
74 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
75 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
76 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
77 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
82 * Local Bus Definitions
86 * FLASH on the Local Bus
87 * Two banks, 8M each, using the CFI driver.
88 * Boot from BR0/OR0 bank at 0xff00_0000
89 * Alternate BR1/OR1 bank at 0xff80_0000
92 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
93 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
94 * Port Size = 16 bits = BRx[19:20] = 10
95 * Use GPCM = BRx[24:26] = 000
98 * 0 4 8 12 16 20 24 28
99 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
100 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
103 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
104 * Reserved ORx[17:18] = 11, confusion here?
106 * ACS = half cycle delay = ORx[21:22] = 11
107 * SCY = 6 = ORx[24:27] = 0110
108 * TRLX = use relaxed timing = ORx[29] = 1
109 * EAD = use external address latch delay = OR[31] = 1
111 * 0 4 8 12 16 20 24 28
112 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
115 #define CFG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
116 #ifdef CONFIG_PHYS_64BIT
117 #define CFG_SYS_FLASH_BASE_PHYS 0xfff000000ull
119 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
122 #define CFG_SYS_FLASH_BANKS_LIST \
123 {CFG_SYS_FLASH_BASE_PHYS + 0x800000, CFG_SYS_FLASH_BASE_PHYS}
126 * SDRAM on the Local Bus
128 #define CFG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
129 #ifdef CONFIG_PHYS_64BIT
130 #define CFG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
132 #define CFG_SYS_LBC_SDRAM_BASE_PHYS CFG_SYS_LBC_SDRAM_BASE
134 #define CFG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
137 * Base Register 2 and Option Register 2 configure SDRAM.
138 * The SDRAM base address, CFG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
141 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
142 * port-size = 32-bits = BR2[19:20] = 11
143 * no parity checking = BR2[21:22] = 00
144 * SDRAM for MSEL = BR2[24:26] = 011
147 * 0 4 8 12 16 20 24 28
148 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
150 * FIXME: CFG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
151 * FIXME: the top 17 bits of BR2.
155 * The SDRAM size in MB, CFG_SYS_LBC_SDRAM_SIZE, is 64.
158 * 64MB mask for AM, OR2[0:7] = 1111 1100
159 * XAM, OR2[17:18] = 11
160 * 9 columns OR2[19-21] = 010
161 * 13 rows OR2[23-25] = 100
162 * EAD set for extra time OR[31] = 1
164 * 0 4 8 12 16 20 24 28
165 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
168 #define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
169 #define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
170 #define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
171 #define CFG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
174 * Common settings for all Local Bus SDRAM commands.
175 * At run time, either BSMA1516 (for CPU 1.1)
176 * or BSMA1617 (for CPU 1.0) (old)
179 #define CFG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
189 * The CADMUS registers are connected to CS3 on CDS.
190 * The new memory map places CADMUS at 0xf8000000.
193 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
194 * port-size = 8-bits = BR[19:20] = 01
195 * no parity checking = BR[21:22] = 00
196 * GPMC for MSEL = BR[24:26] = 000
199 * 0 4 8 12 16 20 24 28
200 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
203 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
204 * disable buffer ctrl OR[19] = 0
208 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
212 * EAD extra time OR[31] = 1
214 * 0 4 8 12 16 20 24 28
215 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
218 #define CADMUS_BASE_ADDR 0xf8000000
219 #ifdef CONFIG_PHYS_64BIT
220 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
222 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
225 #define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
226 #define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
228 #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
231 #define CFG_SYS_NS16550_CLK get_bus_freq(0)
233 #define CFG_SYS_BAUDRATE_TABLE \
234 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
236 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500)
237 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
242 #if !CONFIG_IS_ENABLED(DM_I2C)
243 #define CFG_SYS_I2C_NOPROBES { {0, 0x69} }
248 * Memory space is mapped 1-1, but I/O space must start from 0.
250 #define CFG_SYS_PCI1_MEM_VIRT 0x80000000
251 #ifdef CONFIG_PHYS_64BIT
252 #define CFG_SYS_PCI1_MEM_PHYS 0xc00000000ull
254 #define CFG_SYS_PCI1_MEM_PHYS 0x80000000
256 #define CFG_SYS_PCI1_IO_VIRT 0xe2000000
257 #ifdef CONFIG_PHYS_64BIT
258 #define CFG_SYS_PCI1_IO_PHYS 0xfe2000000ull
260 #define CFG_SYS_PCI1_IO_PHYS 0xe2000000
264 #define CFG_SYS_PCIE1_MEM_VIRT 0xa0000000
265 #ifdef CONFIG_PHYS_64BIT
266 #define CFG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
268 #define CFG_SYS_PCIE1_MEM_PHYS 0xa0000000
270 #define CFG_SYS_PCIE1_IO_VIRT 0xe3000000
271 #ifdef CONFIG_PHYS_64BIT
272 #define CFG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
274 #define CFG_SYS_PCIE1_IO_PHYS 0xe3000000
281 #define CFG_SYS_SRIO1_MEM_VIRT 0xc0000000
282 #ifdef CONFIG_PHYS_64BIT
283 #define CFG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
285 #define CFG_SYS_SRIO1_MEM_PHYS 0xc0000000
287 #define CFG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
289 #if defined(CONFIG_TSEC_ENET)
291 #define CONFIG_TSEC1 1
292 #define CONFIG_TSEC1_NAME "eTSEC0"
293 #define CONFIG_TSEC2 1
294 #define CONFIG_TSEC2_NAME "eTSEC1"
295 #define CONFIG_TSEC3 1
296 #define CONFIG_TSEC3_NAME "eTSEC2"
298 #define CONFIG_TSEC4_NAME "eTSEC3"
299 #undef CONFIG_MPC85XX_FEC
301 #define TSEC1_PHY_ADDR 0
302 #define TSEC2_PHY_ADDR 1
303 #define TSEC3_PHY_ADDR 2
304 #define TSEC4_PHY_ADDR 3
306 #define TSEC1_PHYIDX 0
307 #define TSEC2_PHYIDX 0
308 #define TSEC3_PHYIDX 0
309 #define TSEC4_PHYIDX 0
310 #define TSEC1_FLAGS TSEC_GIGABIT
311 #define TSEC2_FLAGS TSEC_GIGABIT
312 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
313 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
314 #endif /* CONFIG_TSEC_ENET */
317 * Miscellaneous configurable options
321 * For booting Linux, the board info and command line data
322 * have to be in the first 64 MB of memory, since this is
323 * the maximum mapped by the Linux kernel during initialization.
325 #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
328 * Environment Configuration
331 #define CONFIG_IPADDR 192.168.1.253
333 #define CONFIG_HOSTNAME "unknown"
334 #define CONFIG_ROOTPATH "/nfsroot"
335 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
337 #define CONFIG_SERVERIP 192.168.1.1
338 #define CONFIG_GATEWAYIP 192.168.1.1
339 #define CONFIG_NETMASK 255.255.255.0
341 #define CONFIG_EXTRA_ENV_SETTINGS \
342 "hwconfig=fsl_ddr:ecc=off\0" \
344 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
345 "tftpflash=tftpboot $loadaddr $uboot; " \
346 "protect off " __stringify(CONFIG_TEXT_BASE) \
348 "erase " __stringify(CONFIG_TEXT_BASE) \
350 "cp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
352 "protect on " __stringify(CONFIG_TEXT_BASE) \
354 "cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
356 "consoledev=ttyS1\0" \
357 "ramdiskaddr=2000000\0" \
358 "ramdiskfile=ramdisk.uboot\0" \
359 "fdtaddr=1e00000\0" \
360 "fdtfile=mpc8548cds.dtb\0"
362 #endif /* __CONFIG_H */