1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
8 * mpc8548cds board configuration file
10 * Please refer to doc/README.mpc85xxcds for more info.
17 #include <linux/stringify.h>
21 * Only possible on E500 Version 2 or newer cores.
24 #define CFG_SYS_CCSRBAR 0xe0000000
25 #define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
29 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
30 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
32 /* I2C addresses of SPD EEPROMs */
33 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
35 /* Make sure required options are set */
36 #ifndef CONFIG_SPD_EEPROM
37 #error ("CONFIG_SPD_EEPROM is required")
41 * Physical Address Map
44 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
45 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
46 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
47 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
48 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
49 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
50 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
51 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
52 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
53 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
54 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
57 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable
58 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
59 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
60 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
61 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
62 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
63 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
64 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
65 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
66 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
67 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
72 * Local Bus Definitions
76 * FLASH on the Local Bus
77 * Two banks, 8M each, using the CFI driver.
78 * Boot from BR0/OR0 bank at 0xff00_0000
79 * Alternate BR1/OR1 bank at 0xff80_0000
82 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
83 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
84 * Port Size = 16 bits = BRx[19:20] = 10
85 * Use GPCM = BRx[24:26] = 000
88 * 0 4 8 12 16 20 24 28
89 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
90 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
93 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
94 * Reserved ORx[17:18] = 11, confusion here?
96 * ACS = half cycle delay = ORx[21:22] = 11
97 * SCY = 6 = ORx[24:27] = 0110
98 * TRLX = use relaxed timing = ORx[29] = 1
99 * EAD = use external address latch delay = OR[31] = 1
101 * 0 4 8 12 16 20 24 28
102 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
105 #define CFG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
106 #ifdef CONFIG_PHYS_64BIT
107 #define CFG_SYS_FLASH_BASE_PHYS 0xfff000000ull
109 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
112 #define CFG_SYS_FLASH_BANKS_LIST \
113 {CFG_SYS_FLASH_BASE_PHYS + 0x800000, CFG_SYS_FLASH_BASE_PHYS}
116 * SDRAM on the Local Bus
118 #define CFG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
119 #ifdef CONFIG_PHYS_64BIT
120 #define CFG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
122 #define CFG_SYS_LBC_SDRAM_BASE_PHYS CFG_SYS_LBC_SDRAM_BASE
124 #define CFG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
127 * Base Register 2 and Option Register 2 configure SDRAM.
128 * The SDRAM base address, CFG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
131 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
132 * port-size = 32-bits = BR2[19:20] = 11
133 * no parity checking = BR2[21:22] = 00
134 * SDRAM for MSEL = BR2[24:26] = 011
137 * 0 4 8 12 16 20 24 28
138 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
140 * FIXME: CFG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
141 * FIXME: the top 17 bits of BR2.
145 * The SDRAM size in MB, CFG_SYS_LBC_SDRAM_SIZE, is 64.
148 * 64MB mask for AM, OR2[0:7] = 1111 1100
149 * XAM, OR2[17:18] = 11
150 * 9 columns OR2[19-21] = 010
151 * 13 rows OR2[23-25] = 100
152 * EAD set for extra time OR[31] = 1
154 * 0 4 8 12 16 20 24 28
155 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
158 #define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
159 #define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
160 #define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
161 #define CFG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
164 * Common settings for all Local Bus SDRAM commands.
165 * At run time, either BSMA1516 (for CPU 1.1)
166 * or BSMA1617 (for CPU 1.0) (old)
169 #define CFG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
179 * The CADMUS registers are connected to CS3 on CDS.
180 * The new memory map places CADMUS at 0xf8000000.
183 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
184 * port-size = 8-bits = BR[19:20] = 01
185 * no parity checking = BR[21:22] = 00
186 * GPMC for MSEL = BR[24:26] = 000
189 * 0 4 8 12 16 20 24 28
190 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
193 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
194 * disable buffer ctrl OR[19] = 0
198 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
202 * EAD extra time OR[31] = 1
204 * 0 4 8 12 16 20 24 28
205 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
208 #define CADMUS_BASE_ADDR 0xf8000000
209 #ifdef CONFIG_PHYS_64BIT
210 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
212 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
215 #define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
216 #define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
218 #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
221 #define CFG_SYS_NS16550_CLK get_bus_freq(0)
223 #define CFG_SYS_BAUDRATE_TABLE \
224 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
226 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500)
227 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
232 #if !CONFIG_IS_ENABLED(DM_I2C)
233 #define CFG_SYS_I2C_NOPROBES { {0, 0x69} }
238 * Memory space is mapped 1-1, but I/O space must start from 0.
240 #define CFG_SYS_PCI1_MEM_VIRT 0x80000000
241 #ifdef CONFIG_PHYS_64BIT
242 #define CFG_SYS_PCI1_MEM_PHYS 0xc00000000ull
244 #define CFG_SYS_PCI1_MEM_PHYS 0x80000000
246 #define CFG_SYS_PCI1_IO_VIRT 0xe2000000
247 #ifdef CONFIG_PHYS_64BIT
248 #define CFG_SYS_PCI1_IO_PHYS 0xfe2000000ull
250 #define CFG_SYS_PCI1_IO_PHYS 0xe2000000
254 #define CFG_SYS_PCIE1_MEM_VIRT 0xa0000000
255 #ifdef CONFIG_PHYS_64BIT
256 #define CFG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
258 #define CFG_SYS_PCIE1_MEM_PHYS 0xa0000000
260 #define CFG_SYS_PCIE1_IO_VIRT 0xe3000000
261 #ifdef CONFIG_PHYS_64BIT
262 #define CFG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
264 #define CFG_SYS_PCIE1_IO_PHYS 0xe3000000
271 #define CFG_SYS_SRIO1_MEM_VIRT 0xc0000000
272 #ifdef CONFIG_PHYS_64BIT
273 #define CFG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
275 #define CFG_SYS_SRIO1_MEM_PHYS 0xc0000000
277 #define CFG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
280 * Miscellaneous configurable options
284 * For booting Linux, the board info and command line data
285 * have to be in the first 64 MB of memory, since this is
286 * the maximum mapped by the Linux kernel during initialization.
288 #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
291 * Environment Configuration
294 #define CFG_EXTRA_ENV_SETTINGS \
295 "hwconfig=fsl_ddr:ecc=off\0" \
297 "uboot=" CONFIG_UBOOTPATH "\0" \
298 "tftpflash=tftpboot $loadaddr $uboot; " \
299 "protect off " __stringify(CONFIG_TEXT_BASE) \
301 "erase " __stringify(CONFIG_TEXT_BASE) \
303 "cp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
305 "protect on " __stringify(CONFIG_TEXT_BASE) \
307 "cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
309 "consoledev=ttyS1\0" \
310 "ramdiskaddr=2000000\0" \
311 "ramdiskfile=ramdisk.uboot\0" \
312 "fdtaddr=1e00000\0" \
313 "fdtfile=mpc8548cds.dtb\0"
315 #endif /* __CONFIG_H */