1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
8 * mpc8548cds board configuration file
10 * Please refer to doc/README.mpc85xxcds for more info.
16 #define CONFIG_SYS_SRIO
17 #define CONFIG_SRIO1 /* SRIO port 1 */
19 #define CONFIG_PCI1 /* PCI controller 1 */
20 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
22 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
24 #define CONFIG_ENV_OVERWRITE
25 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
27 #define CONFIG_FSL_VIA
30 #include <linux/stringify.h>
31 extern unsigned long get_clock_freq(void);
33 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
36 * These can be toggled for performance analysis, otherwise use default.
38 #define CONFIG_L2_CACHE /* toggle L2 cache */
39 #define CONFIG_BTB /* toggle branch predition */
42 * Only possible on E500 Version 2 or newer cores.
44 #define CONFIG_ENABLE_36BIT_PHYS 1
46 #define CONFIG_SYS_CCSRBAR 0xe0000000
47 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
50 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
51 #define CONFIG_DDR_SPD
53 #define CONFIG_DDR_ECC
54 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
55 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
57 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
58 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
60 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
61 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
63 /* I2C addresses of SPD EEPROMs */
64 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
66 /* Make sure required options are set */
67 #ifndef CONFIG_SPD_EEPROM
68 #error ("CONFIG_SPD_EEPROM is required")
72 * Physical Address Map
75 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
76 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
77 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
78 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
79 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
80 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
81 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
82 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
83 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
84 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
85 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
88 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable
89 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
90 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
91 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
92 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
93 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
94 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
95 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
96 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
97 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
98 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
103 * Local Bus Definitions
107 * FLASH on the Local Bus
108 * Two banks, 8M each, using the CFI driver.
109 * Boot from BR0/OR0 bank at 0xff00_0000
110 * Alternate BR1/OR1 bank at 0xff80_0000
113 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
114 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
115 * Port Size = 16 bits = BRx[19:20] = 10
116 * Use GPCM = BRx[24:26] = 000
117 * Valid = BRx[31] = 1
119 * 0 4 8 12 16 20 24 28
120 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
121 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
124 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
125 * Reserved ORx[17:18] = 11, confusion here?
127 * ACS = half cycle delay = ORx[21:22] = 11
128 * SCY = 6 = ORx[24:27] = 0110
129 * TRLX = use relaxed timing = ORx[29] = 1
130 * EAD = use external address latch delay = OR[31] = 1
132 * 0 4 8 12 16 20 24 28
133 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
136 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
137 #ifdef CONFIG_PHYS_64BIT
138 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
140 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
143 #define CONFIG_SYS_BR0_PRELIM \
144 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
145 #define CONFIG_SYS_BR1_PRELIM \
146 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
148 #define CONFIG_SYS_OR0_PRELIM 0xff806e65
149 #define CONFIG_SYS_OR1_PRELIM 0xff806e65
151 #define CONFIG_SYS_FLASH_BANKS_LIST \
152 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
153 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
154 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
155 #undef CONFIG_SYS_FLASH_CHECKSUM
156 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
157 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
159 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
161 #define CONFIG_SYS_FLASH_EMPTY_INFO
163 #define CONFIG_HWCONFIG /* enable hwconfig */
166 * SDRAM on the Local Bus
168 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
169 #ifdef CONFIG_PHYS_64BIT
170 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
172 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
174 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
177 * Base Register 2 and Option Register 2 configure SDRAM.
178 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
181 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
182 * port-size = 32-bits = BR2[19:20] = 11
183 * no parity checking = BR2[21:22] = 00
184 * SDRAM for MSEL = BR2[24:26] = 011
187 * 0 4 8 12 16 20 24 28
188 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
190 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
191 * FIXME: the top 17 bits of BR2.
194 #define CONFIG_SYS_BR2_PRELIM \
195 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
196 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
199 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
202 * 64MB mask for AM, OR2[0:7] = 1111 1100
203 * XAM, OR2[17:18] = 11
204 * 9 columns OR2[19-21] = 010
205 * 13 rows OR2[23-25] = 100
206 * EAD set for extra time OR[31] = 1
208 * 0 4 8 12 16 20 24 28
209 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
212 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
214 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
215 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
216 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
217 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
220 * Common settings for all Local Bus SDRAM commands.
221 * At run time, either BSMA1516 (for CPU 1.1)
222 * or BSMA1617 (for CPU 1.0) (old)
225 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
235 * The CADMUS registers are connected to CS3 on CDS.
236 * The new memory map places CADMUS at 0xf8000000.
239 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
240 * port-size = 8-bits = BR[19:20] = 01
241 * no parity checking = BR[21:22] = 00
242 * GPMC for MSEL = BR[24:26] = 000
245 * 0 4 8 12 16 20 24 28
246 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
249 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
250 * disable buffer ctrl OR[19] = 0
254 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
258 * EAD extra time OR[31] = 1
260 * 0 4 8 12 16 20 24 28
261 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
264 #define CONFIG_FSL_CADMUS
266 #define CADMUS_BASE_ADDR 0xf8000000
267 #ifdef CONFIG_PHYS_64BIT
268 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
270 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
272 #define CONFIG_SYS_BR3_PRELIM \
273 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
274 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
276 #define CONFIG_SYS_INIT_RAM_LOCK 1
277 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
278 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
280 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
281 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
283 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
284 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
287 #define CONFIG_SYS_NS16550_SERIAL
288 #define CONFIG_SYS_NS16550_REG_SIZE 1
289 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
291 #define CONFIG_SYS_BAUDRATE_TABLE \
292 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
294 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
295 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
300 #ifndef CONFIG_DM_I2C
301 #define CONFIG_SYS_I2C
302 #define CONFIG_SYS_FSL_I2C_SPEED 400000
303 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
304 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
305 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
307 #define CONFIG_SYS_SPD_BUS_NUM 0
308 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
309 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
311 #define CONFIG_SYS_I2C_FSL
314 #define CONFIG_ID_EEPROM
315 #define CONFIG_SYS_I2C_EEPROM_CCID
316 #define CONFIG_SYS_ID_EEPROM
317 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
318 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
322 * Memory space is mapped 1-1, but I/O space must start from 0.
324 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
325 #ifdef CONFIG_PHYS_64BIT
326 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
327 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
329 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
330 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
332 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
333 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
334 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
335 #ifdef CONFIG_PHYS_64BIT
336 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
338 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
340 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
343 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
344 #ifdef CONFIG_PHYS_64BIT
345 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
347 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
349 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
350 #ifdef CONFIG_PHYS_64BIT
351 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
353 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
360 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
361 #ifdef CONFIG_PHYS_64BIT
362 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
364 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
366 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
376 #if defined(CONFIG_PCI)
379 #if !defined(CONFIG_DM_PCI)
380 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
381 #define CONFIG_PCI_INDIRECT_BRIDGE 1
382 #define CONFIG_SYS_PCIE1_NAME "Slot"
383 #ifdef CONFIG_PHYS_64BIT
384 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
386 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
388 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
389 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
390 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
393 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
395 #endif /* CONFIG_PCI */
397 #if defined(CONFIG_TSEC_ENET)
399 #define CONFIG_TSEC1 1
400 #define CONFIG_TSEC1_NAME "eTSEC0"
401 #define CONFIG_TSEC2 1
402 #define CONFIG_TSEC2_NAME "eTSEC1"
403 #define CONFIG_TSEC3 1
404 #define CONFIG_TSEC3_NAME "eTSEC2"
406 #define CONFIG_TSEC4_NAME "eTSEC3"
407 #undef CONFIG_MPC85XX_FEC
409 #define TSEC1_PHY_ADDR 0
410 #define TSEC2_PHY_ADDR 1
411 #define TSEC3_PHY_ADDR 2
412 #define TSEC4_PHY_ADDR 3
414 #define TSEC1_PHYIDX 0
415 #define TSEC2_PHYIDX 0
416 #define TSEC3_PHYIDX 0
417 #define TSEC4_PHYIDX 0
418 #define TSEC1_FLAGS TSEC_GIGABIT
419 #define TSEC2_FLAGS TSEC_GIGABIT
420 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
421 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
423 /* Options are: eTSEC[0-3] */
424 #define CONFIG_ETHPRIME "eTSEC0"
425 #endif /* CONFIG_TSEC_ENET */
431 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
432 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
437 #define CONFIG_BOOTP_BOOTFILESIZE
439 #undef CONFIG_WATCHDOG /* watchdog disabled */
442 * Miscellaneous configurable options
444 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
447 * For booting Linux, the board info and command line data
448 * have to be in the first 64 MB of memory, since this is
449 * the maximum mapped by the Linux kernel during initialization.
451 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
452 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
454 #if defined(CONFIG_CMD_KGDB)
455 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
459 * Environment Configuration
461 #if defined(CONFIG_TSEC_ENET)
462 #define CONFIG_HAS_ETH0
463 #define CONFIG_HAS_ETH1
464 #define CONFIG_HAS_ETH2
465 #define CONFIG_HAS_ETH3
468 #define CONFIG_IPADDR 192.168.1.253
470 #define CONFIG_HOSTNAME "unknown"
471 #define CONFIG_ROOTPATH "/nfsroot"
472 #define CONFIG_BOOTFILE "8548cds/uImage.uboot"
473 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
475 #define CONFIG_SERVERIP 192.168.1.1
476 #define CONFIG_GATEWAYIP 192.168.1.1
477 #define CONFIG_NETMASK 255.255.255.0
479 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
481 #define CONFIG_EXTRA_ENV_SETTINGS \
482 "hwconfig=fsl_ddr:ecc=off\0" \
484 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
485 "tftpflash=tftpboot $loadaddr $uboot; " \
486 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
488 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
490 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
492 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
494 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
496 "consoledev=ttyS1\0" \
497 "ramdiskaddr=2000000\0" \
498 "ramdiskfile=ramdisk.uboot\0" \
499 "fdtaddr=1e00000\0" \
500 "fdtfile=mpc8548cds.dtb\0"
502 #define CONFIG_NFSBOOTCOMMAND \
503 "setenv bootargs root=/dev/nfs rw " \
504 "nfsroot=$serverip:$rootpath " \
505 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
506 "console=$consoledev,$baudrate $othbootargs;" \
507 "tftp $loadaddr $bootfile;" \
508 "tftp $fdtaddr $fdtfile;" \
509 "bootm $loadaddr - $fdtaddr"
511 #define CONFIG_RAMBOOTCOMMAND \
512 "setenv bootargs root=/dev/ram rw " \
513 "console=$consoledev,$baudrate $othbootargs;" \
514 "tftp $ramdiskaddr $ramdiskfile;" \
515 "tftp $loadaddr $bootfile;" \
516 "tftp $fdtaddr $fdtfile;" \
517 "bootm $loadaddr $ramdiskaddr $fdtaddr"
519 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
521 #endif /* __CONFIG_H */