1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
8 * mpc8548cds board configuration file
10 * Please refer to doc/README.mpc85xxcds for more info.
17 #include <linux/stringify.h>
21 * These can be toggled for performance analysis, otherwise use default.
23 #define CONFIG_L2_CACHE /* toggle L2 cache */
26 * Only possible on E500 Version 2 or newer cores.
29 #define CFG_SYS_CCSRBAR 0xe0000000
30 #define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
34 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
36 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
37 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
39 /* I2C addresses of SPD EEPROMs */
40 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
42 /* Make sure required options are set */
43 #ifndef CONFIG_SPD_EEPROM
44 #error ("CONFIG_SPD_EEPROM is required")
48 * Physical Address Map
51 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
52 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
53 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
54 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
55 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
56 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
57 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
58 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
59 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
60 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
61 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
64 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable
65 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
66 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
67 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
68 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
69 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
70 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
71 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
72 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
73 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
74 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
79 * Local Bus Definitions
83 * FLASH on the Local Bus
84 * Two banks, 8M each, using the CFI driver.
85 * Boot from BR0/OR0 bank at 0xff00_0000
86 * Alternate BR1/OR1 bank at 0xff80_0000
89 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
90 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
91 * Port Size = 16 bits = BRx[19:20] = 10
92 * Use GPCM = BRx[24:26] = 000
95 * 0 4 8 12 16 20 24 28
96 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
97 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
100 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
101 * Reserved ORx[17:18] = 11, confusion here?
103 * ACS = half cycle delay = ORx[21:22] = 11
104 * SCY = 6 = ORx[24:27] = 0110
105 * TRLX = use relaxed timing = ORx[29] = 1
106 * EAD = use external address latch delay = OR[31] = 1
108 * 0 4 8 12 16 20 24 28
109 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
112 #define CFG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
113 #ifdef CONFIG_PHYS_64BIT
114 #define CFG_SYS_FLASH_BASE_PHYS 0xfff000000ull
116 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
119 #define CFG_SYS_FLASH_BANKS_LIST \
120 {CFG_SYS_FLASH_BASE_PHYS + 0x800000, CFG_SYS_FLASH_BASE_PHYS}
123 * SDRAM on the Local Bus
125 #define CFG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
126 #ifdef CONFIG_PHYS_64BIT
127 #define CFG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
129 #define CFG_SYS_LBC_SDRAM_BASE_PHYS CFG_SYS_LBC_SDRAM_BASE
131 #define CFG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
134 * Base Register 2 and Option Register 2 configure SDRAM.
135 * The SDRAM base address, CFG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
138 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
139 * port-size = 32-bits = BR2[19:20] = 11
140 * no parity checking = BR2[21:22] = 00
141 * SDRAM for MSEL = BR2[24:26] = 011
144 * 0 4 8 12 16 20 24 28
145 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
147 * FIXME: CFG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
148 * FIXME: the top 17 bits of BR2.
152 * The SDRAM size in MB, CFG_SYS_LBC_SDRAM_SIZE, is 64.
155 * 64MB mask for AM, OR2[0:7] = 1111 1100
156 * XAM, OR2[17:18] = 11
157 * 9 columns OR2[19-21] = 010
158 * 13 rows OR2[23-25] = 100
159 * EAD set for extra time OR[31] = 1
161 * 0 4 8 12 16 20 24 28
162 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
165 #define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
166 #define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
167 #define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
168 #define CFG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
171 * Common settings for all Local Bus SDRAM commands.
172 * At run time, either BSMA1516 (for CPU 1.1)
173 * or BSMA1617 (for CPU 1.0) (old)
176 #define CFG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
186 * The CADMUS registers are connected to CS3 on CDS.
187 * The new memory map places CADMUS at 0xf8000000.
190 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
191 * port-size = 8-bits = BR[19:20] = 01
192 * no parity checking = BR[21:22] = 00
193 * GPMC for MSEL = BR[24:26] = 000
196 * 0 4 8 12 16 20 24 28
197 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
200 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
201 * disable buffer ctrl OR[19] = 0
205 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
209 * EAD extra time OR[31] = 1
211 * 0 4 8 12 16 20 24 28
212 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
215 #define CADMUS_BASE_ADDR 0xf8000000
216 #ifdef CONFIG_PHYS_64BIT
217 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
219 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
222 #define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
223 #define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
225 #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
228 #define CFG_SYS_NS16550_CLK get_bus_freq(0)
230 #define CFG_SYS_BAUDRATE_TABLE \
231 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
233 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500)
234 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
239 #if !CONFIG_IS_ENABLED(DM_I2C)
240 #define CFG_SYS_I2C_NOPROBES { {0, 0x69} }
245 * Memory space is mapped 1-1, but I/O space must start from 0.
247 #define CFG_SYS_PCI1_MEM_VIRT 0x80000000
248 #ifdef CONFIG_PHYS_64BIT
249 #define CFG_SYS_PCI1_MEM_PHYS 0xc00000000ull
251 #define CFG_SYS_PCI1_MEM_PHYS 0x80000000
253 #define CFG_SYS_PCI1_IO_VIRT 0xe2000000
254 #ifdef CONFIG_PHYS_64BIT
255 #define CFG_SYS_PCI1_IO_PHYS 0xfe2000000ull
257 #define CFG_SYS_PCI1_IO_PHYS 0xe2000000
261 #define CFG_SYS_PCIE1_MEM_VIRT 0xa0000000
262 #ifdef CONFIG_PHYS_64BIT
263 #define CFG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
265 #define CFG_SYS_PCIE1_MEM_PHYS 0xa0000000
267 #define CFG_SYS_PCIE1_IO_VIRT 0xe3000000
268 #ifdef CONFIG_PHYS_64BIT
269 #define CFG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
271 #define CFG_SYS_PCIE1_IO_PHYS 0xe3000000
278 #define CFG_SYS_SRIO1_MEM_VIRT 0xc0000000
279 #ifdef CONFIG_PHYS_64BIT
280 #define CFG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
282 #define CFG_SYS_SRIO1_MEM_PHYS 0xc0000000
284 #define CFG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
287 * Miscellaneous configurable options
291 * For booting Linux, the board info and command line data
292 * have to be in the first 64 MB of memory, since this is
293 * the maximum mapped by the Linux kernel during initialization.
295 #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
298 * Environment Configuration
301 #define CONFIG_IPADDR 192.168.1.253
303 #define CONFIG_HOSTNAME "unknown"
304 #define CONFIG_ROOTPATH "/nfsroot"
305 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
307 #define CONFIG_SERVERIP 192.168.1.1
308 #define CONFIG_GATEWAYIP 192.168.1.1
309 #define CONFIG_NETMASK 255.255.255.0
311 #define CONFIG_EXTRA_ENV_SETTINGS \
312 "hwconfig=fsl_ddr:ecc=off\0" \
314 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
315 "tftpflash=tftpboot $loadaddr $uboot; " \
316 "protect off " __stringify(CONFIG_TEXT_BASE) \
318 "erase " __stringify(CONFIG_TEXT_BASE) \
320 "cp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
322 "protect on " __stringify(CONFIG_TEXT_BASE) \
324 "cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
326 "consoledev=ttyS1\0" \
327 "ramdiskaddr=2000000\0" \
328 "ramdiskfile=ramdisk.uboot\0" \
329 "fdtaddr=1e00000\0" \
330 "fdtfile=mpc8548cds.dtb\0"
332 #endif /* __CONFIG_H */