2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * mpc8544ds board configuration file
30 /* High Level Configuration Options */
31 #define CONFIG_BOOKE 1 /* BOOKE */
32 #define CONFIG_E500 1 /* BOOKE e500 family */
33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
34 #define CONFIG_MPC8544 1
35 #define CONFIG_MPC8544DS 1
37 #ifndef CONFIG_SYS_TEXT_BASE
38 #define CONFIG_SYS_TEXT_BASE 0xfff80000
41 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
42 #define CONFIG_PCI1 1 /* PCI controller 1 */
43 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
44 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
45 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
46 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
47 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
48 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
50 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
51 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
53 #define CONFIG_TSEC_ENET /* tsec ethernet support */
54 #define CONFIG_ENV_OVERWRITE
55 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
58 extern unsigned long get_board_sys_clk(unsigned long dummy);
60 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
63 * These can be toggled for performance analysis, otherwise use default.
65 #define CONFIG_L2_CACHE /* toggle L2 cache */
66 #define CONFIG_BTB /* toggle branch predition */
69 * Only possible on E500 Version 2 or newer cores.
71 #define CONFIG_ENABLE_36BIT_PHYS 1
73 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
74 #define CONFIG_SYS_MEMTEST_END 0x00400000
75 #define CONFIG_PANIC_HANG /* do not reset board on panic */
78 * Base addresses -- Note these are effective addresses where the
79 * actual resources get mapped (not physical addresses)
81 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
82 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
83 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
84 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
87 #define CONFIG_FSL_DDR2
88 #undef CONFIG_FSL_DDR_INTERACTIVE
89 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
90 #define CONFIG_DDR_SPD
92 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
93 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
95 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
96 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
97 #define CONFIG_VERY_BIG_RAM
99 #define CONFIG_NUM_DDR_CONTROLLERS 1
100 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
101 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
103 /* I2C addresses of SPD EEPROMs */
104 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
106 /* Make sure required options are set */
107 #ifndef CONFIG_SPD_EEPROM
108 #error ("CONFIG_SPD_EEPROM is required")
111 #undef CONFIG_CLOCKS_IN_MHZ
116 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
118 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
120 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
122 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
123 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
127 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
128 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
130 * Localbus non-cacheable
132 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
133 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
134 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
139 * Local Bus Definitions
141 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
143 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
145 #define CONFIG_SYS_BR0_PRELIM 0xff801001
146 #define CONFIG_SYS_BR1_PRELIM 0xfe801001
148 #define CONFIG_SYS_OR0_PRELIM 0xff806e65
149 #define CONFIG_SYS_OR1_PRELIM 0xff806e65
151 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
153 #define CONFIG_SYS_FLASH_QUIET_TEST
154 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
155 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
156 #undef CONFIG_SYS_FLASH_CHECKSUM
157 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
158 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
159 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
161 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
163 #define CONFIG_FLASH_CFI_DRIVER
164 #define CONFIG_SYS_FLASH_CFI
165 #define CONFIG_SYS_FLASH_EMPTY_INFO
167 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
169 #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
170 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
172 #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
173 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
175 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
176 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */
177 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
178 #define PIXIS_VER 0x1 /* Board version at offset 1 */
179 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
180 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
181 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
183 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
184 #define PIXIS_VCTL 0x10 /* VELA Control Register */
185 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
186 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
187 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
188 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
189 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
190 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
191 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
192 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
193 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
194 #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
195 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
196 #define PIXIS_VSPEED2_TSEC1SER 0x2
197 #define PIXIS_VSPEED2_TSEC3SER 0x1
198 #define PIXIS_VCFGEN1_TSEC1SER 0x20
199 #define PIXIS_VCFGEN1_TSEC3SER 0x40
200 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
201 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
204 #define CONFIG_SYS_INIT_RAM_LOCK 1
205 #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
206 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
209 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
210 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
212 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
213 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
215 /* Serial Port - controlled on board with jumper J8
219 #define CONFIG_CONS_INDEX 1
220 #define CONFIG_SYS_NS16550
221 #define CONFIG_SYS_NS16550_SERIAL
222 #define CONFIG_SYS_NS16550_REG_SIZE 1
223 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
225 #define CONFIG_SYS_BAUDRATE_TABLE \
226 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
228 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
229 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
231 /* Use the HUSH parser */
232 #define CONFIG_SYS_HUSH_PARSER
233 #ifdef CONFIG_SYS_HUSH_PARSER
234 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
237 /* pass open firmware flat tree */
238 #define CONFIG_OF_LIBFDT 1
239 #define CONFIG_OF_BOARD_SETUP 1
240 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
243 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
244 #define CONFIG_HARD_I2C /* I2C with hardware support */
245 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
246 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
247 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
248 #define CONFIG_SYS_I2C_SLAVE 0x7F
249 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
250 #define CONFIG_SYS_I2C_OFFSET 0x3100
254 * Memory space is mapped 1-1, but I/O space must start from 0.
256 #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
257 #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
258 #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
259 #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
261 #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
262 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
263 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
264 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
265 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
266 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
267 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
268 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
270 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
271 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
272 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
273 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
274 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
275 #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
276 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
277 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
278 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
280 /* controller 1, Slot 2,tgtid 2, Base address a000 */
281 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
282 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
283 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
284 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
285 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
286 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
287 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
288 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
290 /* controller 3, direct to uli, tgtid 3, Base address b000 */
291 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
292 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
293 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
294 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
295 #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
296 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
297 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
298 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
299 #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
300 #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
301 #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
302 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
304 #if defined(CONFIG_PCI)
306 /*PCIE video card used*/
307 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
309 /*PCI video card used*/
310 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
315 #if defined(CONFIG_VIDEO)
316 #define CONFIG_BIOSEMU
317 #define CONFIG_CFB_CONSOLE
318 #define CONFIG_VIDEO_SW_CURSOR
319 #define CONFIG_VGA_AS_SINGLE_DEVICE
320 #define CONFIG_ATI_RADEON_FB
321 #define CONFIG_VIDEO_LOGO
322 /*#define CONFIG_CONSOLE_CURSOR*/
323 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
326 #define CONFIG_NET_MULTI
327 #define CONFIG_PCI_PNP /* do pci plug-and-play */
329 #undef CONFIG_EEPRO100
331 #define CONFIG_RTL8139
333 #ifndef CONFIG_PCI_PNP
334 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
335 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
336 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
339 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
340 #define CONFIG_DOS_PARTITION
341 #define CONFIG_SCSI_AHCI
343 #ifdef CONFIG_SCSI_AHCI
344 #define CONFIG_SATA_ULI5288
345 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
346 #define CONFIG_SYS_SCSI_MAX_LUN 1
347 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
348 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
351 #endif /* CONFIG_PCI */
354 #if defined(CONFIG_TSEC_ENET)
356 #ifndef CONFIG_NET_MULTI
357 #define CONFIG_NET_MULTI 1
360 #define CONFIG_MII 1 /* MII PHY management */
361 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
362 #define CONFIG_TSEC1 1
363 #define CONFIG_TSEC1_NAME "eTSEC1"
364 #define CONFIG_TSEC3 1
365 #define CONFIG_TSEC3_NAME "eTSEC3"
367 #define CONFIG_PIXIS_SGMII_CMD
368 #define CONFIG_FSL_SGMII_RISER 1
369 #define SGMII_RISER_PHY_OFFSET 0x1c
371 #define TSEC1_PHY_ADDR 0
372 #define TSEC3_PHY_ADDR 1
374 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
375 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
377 #define TSEC1_PHYIDX 0
378 #define TSEC3_PHYIDX 0
380 #define CONFIG_ETHPRIME "eTSEC1"
382 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
383 #endif /* CONFIG_TSEC_ENET */
388 #define CONFIG_ENV_IS_IN_FLASH 1
389 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
390 #define CONFIG_ENV_ADDR 0xfff80000
392 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000)
394 #define CONFIG_ENV_SIZE 0x2000
395 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
397 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
398 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
403 #define CONFIG_BOOTP_BOOTFILESIZE
404 #define CONFIG_BOOTP_BOOTPATH
405 #define CONFIG_BOOTP_GATEWAY
406 #define CONFIG_BOOTP_HOSTNAME
410 * Command line configuration.
412 #include <config_cmd_default.h>
414 #define CONFIG_CMD_PING
415 #define CONFIG_CMD_I2C
416 #define CONFIG_CMD_MII
417 #define CONFIG_CMD_ELF
418 #define CONFIG_CMD_IRQ
419 #define CONFIG_CMD_SETEXPR
420 #define CONFIG_CMD_REGINFO
422 #if defined(CONFIG_PCI)
423 #define CONFIG_CMD_PCI
424 #define CONFIG_CMD_NET
425 #define CONFIG_CMD_SCSI
426 #define CONFIG_CMD_EXT2
430 #undef CONFIG_WATCHDOG /* watchdog disabled */
433 * Miscellaneous configurable options
435 #define CONFIG_SYS_LONGHELP /* undef to save memory */
436 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
437 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
438 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
439 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
440 #if defined(CONFIG_CMD_KGDB)
441 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
443 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
445 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
446 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
447 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
448 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
451 * For booting Linux, the board info and command line data
452 * have to be in the first 16 MB of memory, since this is
453 * the maximum mapped by the Linux kernel during initialization.
455 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
457 #if defined(CONFIG_CMD_KGDB)
458 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
459 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
463 * Environment Configuration
466 /* The mac addresses for all ethernet interface */
467 #if defined(CONFIG_TSEC_ENET)
468 #define CONFIG_HAS_ETH0
469 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
470 #define CONFIG_HAS_ETH1
471 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
474 #define CONFIG_IPADDR 192.168.1.251
476 #define CONFIG_HOSTNAME 8544ds_unknown
477 #define CONFIG_ROOTPATH /nfs/mpc85xx
478 #define CONFIG_BOOTFILE 8544ds/uImage.uboot
479 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
481 #define CONFIG_SERVERIP 192.168.1.1
482 #define CONFIG_GATEWAYIP 192.168.1.1
483 #define CONFIG_NETMASK 255.255.0.0
485 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
487 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
488 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
490 #define CONFIG_BAUDRATE 115200
492 #define CONFIG_EXTRA_ENV_SETTINGS \
494 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
495 "tftpflash=tftpboot $loadaddr $uboot; " \
496 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
497 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
498 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
499 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
500 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
501 "consoledev=ttyS0\0" \
502 "ramdiskaddr=2000000\0" \
503 "ramdiskfile=8544ds/ramdisk.uboot\0" \
505 "fdtfile=8544ds/mpc8544ds.dtb\0" \
508 #define CONFIG_NFSBOOTCOMMAND \
509 "setenv bootargs root=/dev/nfs rw " \
510 "nfsroot=$serverip:$rootpath " \
511 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
512 "console=$consoledev,$baudrate $othbootargs;" \
513 "tftp $loadaddr $bootfile;" \
514 "tftp $fdtaddr $fdtfile;" \
515 "bootm $loadaddr - $fdtaddr"
517 #define CONFIG_RAMBOOTCOMMAND \
518 "setenv bootargs root=/dev/ram rw " \
519 "console=$consoledev,$baudrate $othbootargs;" \
520 "tftp $ramdiskaddr $ramdiskfile;" \
521 "tftp $loadaddr $bootfile;" \
522 "tftp $fdtaddr $fdtfile;" \
523 "bootm $loadaddr $ramdiskaddr $fdtaddr"
525 #define CONFIG_BOOTCOMMAND \
526 "setenv bootargs root=/dev/$bdev rw " \
527 "console=$consoledev,$baudrate $othbootargs;" \
528 "tftp $loadaddr $bootfile;" \
529 "tftp $fdtaddr $fdtfile;" \
530 "bootm $loadaddr - $fdtaddr"
532 #endif /* __CONFIG_H */