2 * Copyright 2004, 2011 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * mpc8541cds board configuration file
26 * Please refer to doc/README.mpc85xxcds for more info.
32 /* High Level Configuration Options */
33 #define CONFIG_BOOKE 1 /* BOOKE */
34 #define CONFIG_E500 1 /* BOOKE e500 family */
35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
36 #define CONFIG_CPM2 1 /* has CPM2 */
37 #define CONFIG_MPC8541 1 /* MPC8541 specific */
38 #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
40 #define CONFIG_SYS_TEXT_BASE 0xfff80000
43 #define CONFIG_PCI_INDIRECT_BRIDGE
44 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
45 #define CONFIG_TSEC_ENET /* tsec ethernet support */
46 #define CONFIG_ENV_OVERWRITE
48 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
50 #define CONFIG_FSL_VIA
53 extern unsigned long get_clock_freq(void);
55 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
58 * These can be toggled for performance analysis, otherwise use default.
60 #define CONFIG_L2_CACHE /* toggle L2 cache */
61 #define CONFIG_BTB /* toggle branch predition */
63 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
64 #define CONFIG_SYS_MEMTEST_END 0x00400000
66 #define CONFIG_SYS_CCSRBAR 0xe0000000
67 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
70 #define CONFIG_FSL_DDR1
71 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
72 #define CONFIG_DDR_SPD
73 #undef CONFIG_FSL_DDR_INTERACTIVE
75 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
77 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
78 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
80 #define CONFIG_NUM_DDR_CONTROLLERS 1
81 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
82 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
84 /* I2C addresses of SPD EEPROMs */
85 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
88 * Make sure required options are set
90 #ifndef CONFIG_SPD_EEPROM
91 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
94 #undef CONFIG_CLOCKS_IN_MHZ
97 * Local Bus Definitions
101 * FLASH on the Local Bus
102 * Two banks, 8M each, using the CFI driver.
103 * Boot from BR0/OR0 bank at 0xff00_0000
104 * Alternate BR1/OR1 bank at 0xff80_0000
107 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
108 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
109 * Port Size = 16 bits = BRx[19:20] = 10
110 * Use GPCM = BRx[24:26] = 000
111 * Valid = BRx[31] = 1
113 * 0 4 8 12 16 20 24 28
114 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
115 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
118 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
119 * Reserved ORx[17:18] = 11, confusion here?
121 * ACS = half cycle delay = ORx[21:22] = 11
122 * SCY = 6 = ORx[24:27] = 0110
123 * TRLX = use relaxed timing = ORx[29] = 1
124 * EAD = use external address latch delay = OR[31] = 1
126 * 0 4 8 12 16 20 24 28
127 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
130 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
132 #define CONFIG_SYS_BR0_PRELIM 0xff801001
133 #define CONFIG_SYS_BR1_PRELIM 0xff001001
135 #define CONFIG_SYS_OR0_PRELIM 0xff806e65
136 #define CONFIG_SYS_OR1_PRELIM 0xff806e65
138 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
139 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
140 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
141 #undef CONFIG_SYS_FLASH_CHECKSUM
142 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
143 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
145 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
147 #define CONFIG_FLASH_CFI_DRIVER
148 #define CONFIG_SYS_FLASH_CFI
149 #define CONFIG_SYS_FLASH_EMPTY_INFO
153 * SDRAM on the Local Bus
155 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
156 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
159 * Base Register 2 and Option Register 2 configure SDRAM.
160 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
163 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
164 * port-size = 32-bits = BR2[19:20] = 11
165 * no parity checking = BR2[21:22] = 00
166 * SDRAM for MSEL = BR2[24:26] = 011
169 * 0 4 8 12 16 20 24 28
170 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
172 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
173 * FIXME: the top 17 bits of BR2.
176 #define CONFIG_SYS_BR2_PRELIM 0xf0001861
179 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
182 * 64MB mask for AM, OR2[0:7] = 1111 1100
183 * XAM, OR2[17:18] = 11
184 * 9 columns OR2[19-21] = 010
185 * 13 rows OR2[23-25] = 100
186 * EAD set for extra time OR[31] = 1
188 * 0 4 8 12 16 20 24 28
189 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
192 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
194 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
195 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
196 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
197 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
200 * Common settings for all Local Bus SDRAM commands.
201 * At run time, either BSMA1516 (for CPU 1.1)
202 * or BSMA1617 (for CPU 1.0) (old)
205 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
215 * The CADMUS registers are connected to CS3 on CDS.
216 * The new memory map places CADMUS at 0xf8000000.
219 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
220 * port-size = 8-bits = BR[19:20] = 01
221 * no parity checking = BR[21:22] = 00
222 * GPMC for MSEL = BR[24:26] = 000
225 * 0 4 8 12 16 20 24 28
226 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
229 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
230 * disable buffer ctrl OR[19] = 0
234 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
238 * EAD extra time OR[31] = 1
240 * 0 4 8 12 16 20 24 28
241 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
244 #define CONFIG_FSL_CADMUS
246 #define CADMUS_BASE_ADDR 0xf8000000
247 #define CONFIG_SYS_BR3_PRELIM 0xf8000801
248 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
250 #define CONFIG_SYS_INIT_RAM_LOCK 1
251 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
252 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
254 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
255 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
257 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
258 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
261 #define CONFIG_CONS_INDEX 2
262 #define CONFIG_SYS_NS16550
263 #define CONFIG_SYS_NS16550_SERIAL
264 #define CONFIG_SYS_NS16550_REG_SIZE 1
265 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
267 #define CONFIG_SYS_BAUDRATE_TABLE \
268 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
270 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
271 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
273 /* Use the HUSH parser */
274 #define CONFIG_SYS_HUSH_PARSER
275 #ifdef CONFIG_SYS_HUSH_PARSER
278 /* pass open firmware flat tree */
279 #define CONFIG_OF_LIBFDT 1
280 #define CONFIG_OF_BOARD_SETUP 1
281 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
286 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
287 #define CONFIG_HARD_I2C /* I2C with hardware support*/
288 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
289 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
290 #define CONFIG_SYS_I2C_SLAVE 0x7F
291 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
292 #define CONFIG_SYS_I2C_OFFSET 0x3000
295 #define CONFIG_ID_EEPROM
296 #define CONFIG_SYS_I2C_EEPROM_CCID
297 #define CONFIG_SYS_ID_EEPROM
298 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
299 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
303 * Memory space is mapped 1-1, but I/O space must start from 0.
305 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
306 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
307 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
308 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
309 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
310 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
311 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
312 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
314 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
315 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
316 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
317 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
318 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
319 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000
320 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
321 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */
331 #if defined(CONFIG_PCI)
333 #define CONFIG_MPC85XX_PCI2
334 #define CONFIG_PCI_PNP /* do pci plug-and-play */
336 #undef CONFIG_EEPRO100
339 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
340 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
342 #endif /* CONFIG_PCI */
345 #if defined(CONFIG_TSEC_ENET)
347 #define CONFIG_MII 1 /* MII PHY management */
348 #define CONFIG_TSEC1 1
349 #define CONFIG_TSEC1_NAME "TSEC0"
350 #define CONFIG_TSEC2 1
351 #define CONFIG_TSEC2_NAME "TSEC1"
352 #define TSEC1_PHY_ADDR 0
353 #define TSEC2_PHY_ADDR 1
354 #define TSEC1_PHYIDX 0
355 #define TSEC2_PHYIDX 0
356 #define TSEC1_FLAGS TSEC_GIGABIT
357 #define TSEC2_FLAGS TSEC_GIGABIT
359 /* Options are: TSEC[0-1] */
360 #define CONFIG_ETHPRIME "TSEC0"
362 #endif /* CONFIG_TSEC_ENET */
367 #define CONFIG_ENV_IS_IN_FLASH 1
368 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
369 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
370 #define CONFIG_ENV_SIZE 0x2000
372 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
373 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
378 #define CONFIG_BOOTP_BOOTFILESIZE
379 #define CONFIG_BOOTP_BOOTPATH
380 #define CONFIG_BOOTP_GATEWAY
381 #define CONFIG_BOOTP_HOSTNAME
385 * Command line configuration.
387 #include <config_cmd_default.h>
389 #define CONFIG_CMD_PING
390 #define CONFIG_CMD_I2C
391 #define CONFIG_CMD_MII
392 #define CONFIG_CMD_ELF
393 #define CONFIG_CMD_IRQ
394 #define CONFIG_CMD_SETEXPR
395 #define CONFIG_CMD_REGINFO
397 #if defined(CONFIG_PCI)
398 #define CONFIG_CMD_PCI
402 #undef CONFIG_WATCHDOG /* watchdog disabled */
405 * Miscellaneous configurable options
407 #define CONFIG_SYS_LONGHELP /* undef to save memory */
408 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
409 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
410 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
411 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
412 #if defined(CONFIG_CMD_KGDB)
413 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
415 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
417 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
418 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
419 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
420 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
423 * For booting Linux, the board info and command line data
424 * have to be in the first 64 MB of memory, since this is
425 * the maximum mapped by the Linux kernel during initialization.
427 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
428 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
430 #if defined(CONFIG_CMD_KGDB)
431 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
432 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
436 * Environment Configuration
439 /* The mac addresses for all ethernet interface */
440 #if defined(CONFIG_TSEC_ENET)
441 #define CONFIG_HAS_ETH0
442 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
443 #define CONFIG_HAS_ETH1
444 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
445 #define CONFIG_HAS_ETH2
446 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
449 #define CONFIG_IPADDR 192.168.1.253
451 #define CONFIG_HOSTNAME unknown
452 #define CONFIG_ROOTPATH "/nfsroot"
453 #define CONFIG_BOOTFILE "your.uImage"
455 #define CONFIG_SERVERIP 192.168.1.1
456 #define CONFIG_GATEWAYIP 192.168.1.1
457 #define CONFIG_NETMASK 255.255.255.0
459 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
461 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
462 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
464 #define CONFIG_BAUDRATE 115200
466 #define CONFIG_EXTRA_ENV_SETTINGS \
468 "consoledev=ttyS1\0" \
469 "ramdiskaddr=600000\0" \
470 "ramdiskfile=your.ramdisk.u-boot\0" \
472 "fdtfile=your.fdt.dtb\0"
474 #define CONFIG_NFSBOOTCOMMAND \
475 "setenv bootargs root=/dev/nfs rw " \
476 "nfsroot=$serverip:$rootpath " \
477 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
478 "console=$consoledev,$baudrate $othbootargs;" \
479 "tftp $loadaddr $bootfile;" \
480 "tftp $fdtaddr $fdtfile;" \
481 "bootm $loadaddr - $fdtaddr"
483 #define CONFIG_RAMBOOTCOMMAND \
484 "setenv bootargs root=/dev/ram rw " \
485 "console=$consoledev,$baudrate $othbootargs;" \
486 "tftp $ramdiskaddr $ramdiskfile;" \
487 "tftp $loadaddr $bootfile;" \
488 "bootm $loadaddr $ramdiskaddr"
490 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
492 #endif /* __CONFIG_H */