2 * Copyright 2004 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * mpc8541cds board configuration file
26 * Please refer to doc/README.mpc85xxcds for more info.
32 /* High Level Configuration Options */
33 #define CONFIG_BOOKE 1 /* BOOKE */
34 #define CONFIG_E500 1 /* BOOKE e500 family */
35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
36 #define CONFIG_CPM2 1 /* has CPM2 */
37 #define CONFIG_MPC8541 1 /* MPC8541 specific */
38 #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
41 #define CONFIG_TSEC_ENET /* tsec ethernet support */
42 #define CONFIG_ENV_OVERWRITE
43 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
44 #define CONFIG_DDR_DLL /* possible DLL fix needed */
45 #undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
47 #define CONFIG_DDR_ECC /* only for ECC DDR module */
48 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
52 * When initializing flash, if we cannot find the manufacturer ID,
53 * assume this is the AMD flash associated with the CDS board.
54 * This allows booting from a promjet.
56 #define CONFIG_ASSUME_AMD_FLASH
58 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
61 extern unsigned long get_clock_freq(void);
63 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
66 * These can be toggled for performance analysis, otherwise use default.
68 #define CONFIG_L2_CACHE /* toggle L2 cache */
69 #define CONFIG_BTB /* toggle branch predition */
70 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
72 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
74 #undef CFG_DRAM_TEST /* memory test, takes time */
75 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */
76 #define CFG_MEMTEST_END 0x00400000
79 * Base addresses -- Note these are effective addresses where the
80 * actual resources get mapped (not physical addresses)
82 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
83 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
84 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
89 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
90 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
92 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
95 * Make sure required options are set
97 #ifndef CONFIG_SPD_EEPROM
98 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
101 #undef CONFIG_CLOCKS_IN_MHZ
105 * Local Bus Definitions
109 * FLASH on the Local Bus
110 * Two banks, 8M each, using the CFI driver.
111 * Boot from BR0/OR0 bank at 0xff00_0000
112 * Alternate BR1/OR1 bank at 0xff80_0000
115 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
116 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
117 * Port Size = 16 bits = BRx[19:20] = 10
118 * Use GPCM = BRx[24:26] = 000
119 * Valid = BRx[31] = 1
121 * 0 4 8 12 16 20 24 28
122 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
123 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
126 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
127 * Reserved ORx[17:18] = 11, confusion here?
129 * ACS = half cycle delay = ORx[21:22] = 11
130 * SCY = 6 = ORx[24:27] = 0110
131 * TRLX = use relaxed timing = ORx[29] = 1
132 * EAD = use external address latch delay = OR[31] = 1
134 * 0 4 8 12 16 20 24 28
135 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
138 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */
140 #define CFG_BR0_PRELIM 0xff801001
141 #define CFG_BR1_PRELIM 0xff001001
143 #define CFG_OR0_PRELIM 0xff806e65
144 #define CFG_OR1_PRELIM 0xff806e65
146 #define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
147 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */
148 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */
149 #undef CFG_FLASH_CHECKSUM
150 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
151 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
153 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
155 #define CFG_FLASH_CFI_DRIVER
156 #define CFG_FLASH_CFI
157 #define CFG_FLASH_EMPTY_INFO
161 * SDRAM on the Local Bus
163 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
164 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
167 * Base Register 2 and Option Register 2 configure SDRAM.
168 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
171 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
172 * port-size = 32-bits = BR2[19:20] = 11
173 * no parity checking = BR2[21:22] = 00
174 * SDRAM for MSEL = BR2[24:26] = 011
177 * 0 4 8 12 16 20 24 28
178 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
180 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
181 * FIXME: the top 17 bits of BR2.
184 #define CFG_BR2_PRELIM 0xf0001861
187 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
190 * 64MB mask for AM, OR2[0:7] = 1111 1100
191 * XAM, OR2[17:18] = 11
192 * 9 columns OR2[19-21] = 010
193 * 13 rows OR2[23-25] = 100
194 * EAD set for extra time OR[31] = 1
196 * 0 4 8 12 16 20 24 28
197 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
200 #define CFG_OR2_PRELIM 0xfc006901
202 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
203 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */
204 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
205 #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
210 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
211 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
212 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
213 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
214 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
215 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
216 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
217 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
218 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
219 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
221 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
222 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
223 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
224 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
225 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
226 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
227 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
228 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
231 * Common settings for all Local Bus SDRAM commands.
232 * At run time, either BSMA1516 (for CPU 1.1)
233 * or BSMA1617 (for CPU 1.0) (old)
236 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
237 | CFG_LBC_LSDMR_PRETOACT7 \
238 | CFG_LBC_LSDMR_ACTTORW7 \
239 | CFG_LBC_LSDMR_BL8 \
240 | CFG_LBC_LSDMR_WRC4 \
241 | CFG_LBC_LSDMR_CL3 \
242 | CFG_LBC_LSDMR_RFEN \
246 * The CADMUS registers are connected to CS3 on CDS.
247 * The new memory map places CADMUS at 0xf8000000.
250 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
251 * port-size = 8-bits = BR[19:20] = 01
252 * no parity checking = BR[21:22] = 00
253 * GPMC for MSEL = BR[24:26] = 000
256 * 0 4 8 12 16 20 24 28
257 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
260 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
261 * disable buffer ctrl OR[19] = 0
265 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
269 * EAD extra time OR[31] = 1
271 * 0 4 8 12 16 20 24 28
272 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
275 #define CADMUS_BASE_ADDR 0xf8000000
276 #define CFG_BR3_PRELIM 0xf8000801
277 #define CFG_OR3_PRELIM 0xfff00ff7
279 #define CONFIG_L1_INIT_RAM
280 #define CFG_INIT_RAM_LOCK 1
281 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
282 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
284 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
285 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
286 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
288 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
289 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
292 #define CONFIG_CONS_INDEX 2
293 #undef CONFIG_SERIAL_SOFTWARE_FIFO
295 #define CFG_NS16550_SERIAL
296 #define CFG_NS16550_REG_SIZE 1
297 #define CFG_NS16550_CLK get_bus_freq(0)
299 #define CFG_BAUDRATE_TABLE \
300 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
302 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
303 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
305 /* Use the HUSH parser */
306 #define CFG_HUSH_PARSER
307 #ifdef CFG_HUSH_PARSER
308 #define CFG_PROMPT_HUSH_PS2 "> "
311 /* pass open firmware flat tree */
312 #define CONFIG_OF_FLAT_TREE 1
313 #define CONFIG_OF_BOARD_SETUP 1
315 /* maximum size of the flat tree (8K) */
316 #define OF_FLAT_TREE_MAX_SIZE 8192
318 #define OF_CPU "PowerPC,8541@0"
319 #define OF_SOC "soc8541@e0000000"
320 #define OF_TBCLK (bd->bi_busfreq / 8)
321 #define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600"
326 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
327 #define CONFIG_HARD_I2C /* I2C with hardware support*/
328 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
329 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
330 #define CFG_I2C_EEPROM_ADDR 0x57
331 #define CFG_I2C_SLAVE 0x7F
332 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
333 #define CFG_I2C_OFFSET 0x3000
337 * Memory space is mapped 1-1, but I/O space must start from 0.
339 #define CFG_PCI1_MEM_BASE 0x80000000
340 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
341 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
342 #define CFG_PCI1_IO_BASE 0x00000000
343 #define CFG_PCI1_IO_PHYS 0xe2000000
344 #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
346 #define CFG_PCI2_MEM_BASE 0xa0000000
347 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
348 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
349 #define CFG_PCI2_IO_BASE 0x00000000
350 #define CFG_PCI2_IO_PHYS 0xe2100000
351 #define CFG_PCI2_IO_SIZE 0x100000 /* 1M */
354 #if defined(CONFIG_PCI)
356 #define CONFIG_MPC85XX_PCI2
357 #define CONFIG_NET_MULTI
358 #define CONFIG_PCI_PNP /* do pci plug-and-play */
360 #undef CONFIG_EEPRO100
363 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
364 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
366 #endif /* CONFIG_PCI */
369 #if defined(CONFIG_TSEC_ENET)
371 #ifndef CONFIG_NET_MULTI
372 #define CONFIG_NET_MULTI 1
375 #define CONFIG_MII 1 /* MII PHY management */
376 #define CONFIG_TSEC1 1
377 #define CONFIG_TSEC1_NAME "TSEC0"
378 #define CONFIG_TSEC2 1
379 #define CONFIG_TSEC2_NAME "TSEC1"
380 #undef CONFIG_MPC85XX_FEC
381 #define TSEC1_PHY_ADDR 0
382 #define TSEC2_PHY_ADDR 1
383 #define FEC_PHY_ADDR 3
384 #define TSEC1_PHYIDX 0
385 #define TSEC2_PHYIDX 0
388 /* Options are: TSEC[0-1] */
389 #define CONFIG_ETHPRIME "TSEC0"
391 #endif /* CONFIG_TSEC_ENET */
396 #define CFG_ENV_IS_IN_FLASH 1
397 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
398 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
399 #define CFG_ENV_SIZE 0x2000
401 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
402 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
405 * Command line configuration.
407 #include <config_cmd_default.h>
409 #define CONFIG_CMD_PING
410 #define CONFIG_CMD_I2C
411 #define CONFIG_CMD_MII
413 #if defined(CONFIG_PCI)
414 #define CONFIG_CMD_PCI
418 #undef CONFIG_WATCHDOG /* watchdog disabled */
421 * Miscellaneous configurable options
423 #define CFG_LONGHELP /* undef to save memory */
424 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
425 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
426 #if defined(CONFIG_CMD_KGDB)
427 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
429 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
431 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
432 #define CFG_MAXARGS 16 /* max number of command args */
433 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
434 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
437 * For booting Linux, the board info and command line data
438 * have to be in the first 8 MB of memory, since this is
439 * the maximum mapped by the Linux kernel during initialization.
441 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
443 /* Cache Configuration */
444 #define CFG_DCACHE_SIZE 32768
445 #define CFG_CACHELINE_SIZE 32
446 #if defined(CONFIG_CMD_KGDB)
447 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
451 * Internal Definitions
455 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
456 #define BOOTFLAG_WARM 0x02 /* Software reboot */
458 #if defined(CONFIG_CMD_KGDB)
459 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
460 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
464 * Environment Configuration
467 /* The mac addresses for all ethernet interface */
468 #if defined(CONFIG_TSEC_ENET)
469 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
470 #define CONFIG_HAS_ETH1
471 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
472 #define CONFIG_HAS_ETH2
473 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
476 #define CONFIG_IPADDR 192.168.1.253
478 #define CONFIG_HOSTNAME unknown
479 #define CONFIG_ROOTPATH /nfsroot
480 #define CONFIG_BOOTFILE your.uImage
482 #define CONFIG_SERVERIP 192.168.1.1
483 #define CONFIG_GATEWAYIP 192.168.1.1
484 #define CONFIG_NETMASK 255.255.255.0
486 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
488 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
489 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
491 #define CONFIG_BAUDRATE 115200
493 #define CONFIG_EXTRA_ENV_SETTINGS \
495 "consoledev=ttyS1\0" \
496 "ramdiskaddr=600000\0" \
497 "ramdiskfile=your.ramdisk.u-boot\0" \
499 "fdtfile=your.fdt.dtb\0"
501 #define CONFIG_NFSBOOTCOMMAND \
502 "setenv bootargs root=/dev/nfs rw " \
503 "nfsroot=$serverip:$rootpath " \
504 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
505 "console=$consoledev,$baudrate $othbootargs;" \
506 "tftp $loadaddr $bootfile;" \
507 "tftp $fdtaddr $fdtfile;" \
508 "bootm $loadaddr - $fdtaddr"
510 #define CONFIG_RAMBOOTCOMMAND \
511 "setenv bootargs root=/dev/ram rw " \
512 "console=$consoledev,$baudrate $othbootargs;" \
513 "tftp $ramdiskaddr $ramdiskfile;" \
514 "tftp $loadaddr $bootfile;" \
515 "bootm $loadaddr $ramdiskaddr"
517 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
519 #endif /* __CONFIG_H */