1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004, 2011 Freescale Semiconductor.
4 * (C) Copyright 2002,2003 Motorola,Inc.
5 * Xianghua Xiao <X.Xiao@motorola.com>
9 * mpc8540ads board configuration file
11 * Please refer to doc/README.mpc85xx for more info.
13 * Make sure you change the MAC address and other network params first,
14 * search for CONFIG_SERVERIP, etc in this file.
21 * default CCARBAR is at 0xff700000
22 * assume U-Boot is less than 0.5MB
25 #ifndef CONFIG_HAS_FEC
26 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */
32 * Two valid values are:
36 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
37 * is likely the desired value here, so that is now the default.
38 * The board, however, can run at 66MHz. In any event, this value
39 * must match the settings of some switches. Details can be found
40 * in the README.mpc85xxads.
42 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
43 * 33MHz to accommodate, based on a PCI pin.
44 * Note that PCI-X won't work at 33MHz.
47 #ifndef CONFIG_SYS_CLK_FREQ
48 #define CONFIG_SYS_CLK_FREQ 33000000
52 * These can be toggled for performance analysis, otherwise use default.
54 #define CONFIG_L2_CACHE /* toggle L2 cache */
55 #define CONFIG_BTB /* toggle branch predition */
57 #define CONFIG_SYS_CCSRBAR 0xe0000000
58 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
61 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
63 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
65 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
66 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
68 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
69 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
71 /* I2C addresses of SPD EEPROMs */
72 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
74 /* These are used when DDR doesn't use SPD. */
75 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
76 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
77 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
78 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
79 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
80 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
81 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
82 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
85 * SDRAM on the Local Bus
87 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
88 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
90 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
92 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
93 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
94 #undef CONFIG_SYS_FLASH_CHECKSUM
95 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
96 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
98 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
100 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
101 #define CONFIG_SYS_RAMBOOT
103 #undef CONFIG_SYS_RAMBOOT
106 #define CONFIG_SYS_FLASH_EMPTY_INFO
109 * Local Bus Definitions
113 * Base Register 2 and Option Register 2 configure SDRAM.
114 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
117 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
118 * port-size = 32-bits = BR2[19:20] = 11
119 * no parity checking = BR2[21:22] = 00
120 * SDRAM for MSEL = BR2[24:26] = 011
123 * 0 4 8 12 16 20 24 28
124 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
126 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
127 * FIXME: the top 17 bits of BR2.
131 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
134 * 64MB mask for AM, OR2[0:7] = 1111 1100
135 * XAM, OR2[17:18] = 11
136 * 9 columns OR2[19-21] = 010
137 * 13 rows OR2[23-25] = 100
138 * EAD set for extra time OR[31] = 1
140 * 0 4 8 12 16 20 24 28
141 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
144 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
145 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
146 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
147 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
149 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
160 * SDRAM Controller configuration sequence.
162 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
163 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
164 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
165 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
166 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
169 * 32KB, 8-bit wide for ADS config reg
171 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
173 #define CONFIG_SYS_INIT_RAM_LOCK 1
174 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
175 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
177 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
178 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
180 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
183 #define CONFIG_SYS_NS16550_SERIAL
184 #define CONFIG_SYS_NS16550_REG_SIZE 1
185 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
187 #define CONFIG_SYS_BAUDRATE_TABLE \
188 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
190 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
191 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
196 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
199 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
200 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
201 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
202 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
206 * Memory space is mapped 1-1, but I/O space must start from 0.
208 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
209 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
210 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
211 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
212 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
213 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
214 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
215 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
217 #if defined(CONFIG_PCI)
219 #if !defined(CONFIG_PCI_PNP)
220 #define PCI_ENET0_IOADDR 0xe0000000
221 #define PCI_ENET0_MEMADDR 0xe0000000
222 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
225 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
227 #endif /* CONFIG_PCI */
229 #if defined(CONFIG_TSEC_ENET)
231 #define CONFIG_TSEC1 1
232 #define CONFIG_TSEC1_NAME "TSEC0"
233 #define CONFIG_TSEC2 1
234 #define CONFIG_TSEC2_NAME "TSEC1"
235 #define TSEC1_PHY_ADDR 0
236 #define TSEC2_PHY_ADDR 1
237 #define TSEC1_PHYIDX 0
238 #define TSEC2_PHYIDX 0
239 #define TSEC1_FLAGS TSEC_GIGABIT
240 #define TSEC2_FLAGS TSEC_GIGABIT
243 #define CONFIG_MPC85XX_FEC 1
244 #define CONFIG_MPC85XX_FEC_NAME "FEC"
245 #define FEC_PHY_ADDR 3
250 /* Options are: TSEC[0-1], FEC */
251 #define CONFIG_ETHPRIME "TSEC0"
253 #endif /* CONFIG_TSEC_ENET */
259 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
260 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
265 #define CONFIG_BOOTP_BOOTFILESIZE
268 * Miscellaneous configurable options
272 * For booting Linux, the board info and command line data
273 * have to be in the first 64 MB of memory, since this is
274 * the maximum mapped by the Linux kernel during initialization.
276 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
277 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
280 * Environment Configuration
283 /* The mac addresses for all ethernet interface */
284 #if defined(CONFIG_TSEC_ENET)
285 #define CONFIG_HAS_ETH0
286 #define CONFIG_HAS_ETH1
287 #define CONFIG_HAS_ETH2
290 #define CONFIG_IPADDR 192.168.1.253
292 #define CONFIG_HOSTNAME "unknown"
293 #define CONFIG_ROOTPATH "/nfsroot"
294 #define CONFIG_BOOTFILE "your.uImage"
296 #define CONFIG_SERVERIP 192.168.1.1
297 #define CONFIG_GATEWAYIP 192.168.1.1
298 #define CONFIG_NETMASK 255.255.255.0
300 #define CONFIG_EXTRA_ENV_SETTINGS \
302 "consoledev=ttyS0\0" \
303 "ramdiskaddr=1000000\0" \
304 "ramdiskfile=your.ramdisk.u-boot\0" \
306 "fdtfile=your.fdt.dtb\0"
308 #endif /* __CONFIG_H */