2 * Copyright 2004, 2011 Freescale Semiconductor.
3 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 * mpc8540ads board configuration file
12 * Please refer to doc/README.mpc85xx for more info.
14 * Make sure you change the MAC address and other network params first,
15 * search for CONFIG_SERVERIP, etc in this file.
21 /* High Level Configuration Options */
22 #define CONFIG_BOOKE 1 /* BOOKE */
23 #define CONFIG_E500 1 /* BOOKE e500 family */
26 * default CCARBAR is at 0xff700000
27 * assume U-Boot is less than 0.5MB
29 #define CONFIG_SYS_TEXT_BASE 0xfff80000
31 #ifndef CONFIG_HAS_FEC
32 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */
35 #define CONFIG_PCI_INDIRECT_BRIDGE
36 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
37 #define CONFIG_TSEC_ENET /* tsec ethernet support */
38 #define CONFIG_ENV_OVERWRITE
39 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
44 * Two valid values are:
48 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
49 * is likely the desired value here, so that is now the default.
50 * The board, however, can run at 66MHz. In any event, this value
51 * must match the settings of some switches. Details can be found
52 * in the README.mpc85xxads.
54 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
55 * 33MHz to accommodate, based on a PCI pin.
56 * Note that PCI-X won't work at 33MHz.
59 #ifndef CONFIG_SYS_CLK_FREQ
60 #define CONFIG_SYS_CLK_FREQ 33000000
64 * These can be toggled for performance analysis, otherwise use default.
66 #define CONFIG_L2_CACHE /* toggle L2 cache */
67 #define CONFIG_BTB /* toggle branch predition */
69 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
70 #define CONFIG_SYS_MEMTEST_END 0x00400000
72 #define CONFIG_SYS_CCSRBAR 0xe0000000
73 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
76 #define CONFIG_SYS_FSL_DDR1
77 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
78 #define CONFIG_DDR_SPD
79 #undef CONFIG_FSL_DDR_INTERACTIVE
81 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
83 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
84 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
86 #define CONFIG_NUM_DDR_CONTROLLERS 1
87 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
88 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
90 /* I2C addresses of SPD EEPROMs */
91 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
93 /* These are used when DDR doesn't use SPD. */
94 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
95 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
96 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
97 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
98 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
99 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
100 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
101 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
104 * SDRAM on the Local Bus
106 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
107 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
109 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
110 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
112 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
113 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
114 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
115 #undef CONFIG_SYS_FLASH_CHECKSUM
116 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
117 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
119 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
121 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
122 #define CONFIG_SYS_RAMBOOT
124 #undef CONFIG_SYS_RAMBOOT
127 #define CONFIG_FLASH_CFI_DRIVER
128 #define CONFIG_SYS_FLASH_CFI
129 #define CONFIG_SYS_FLASH_EMPTY_INFO
131 #undef CONFIG_CLOCKS_IN_MHZ
134 * Local Bus Definitions
138 * Base Register 2 and Option Register 2 configure SDRAM.
139 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
142 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
143 * port-size = 32-bits = BR2[19:20] = 11
144 * no parity checking = BR2[21:22] = 00
145 * SDRAM for MSEL = BR2[24:26] = 011
148 * 0 4 8 12 16 20 24 28
149 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
151 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
152 * FIXME: the top 17 bits of BR2.
155 #define CONFIG_SYS_BR2_PRELIM 0xf0001861
158 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
161 * 64MB mask for AM, OR2[0:7] = 1111 1100
162 * XAM, OR2[17:18] = 11
163 * 9 columns OR2[19-21] = 010
164 * 13 rows OR2[23-25] = 100
165 * EAD set for extra time OR[31] = 1
167 * 0 4 8 12 16 20 24 28
168 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
171 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
173 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
174 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
175 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
176 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
178 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
189 * SDRAM Controller configuration sequence.
191 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
192 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
193 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
194 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
195 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
198 * 32KB, 8-bit wide for ADS config reg
200 #define CONFIG_SYS_BR4_PRELIM 0xf8000801
201 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
202 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
204 #define CONFIG_SYS_INIT_RAM_LOCK 1
205 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
206 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
208 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
209 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
211 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
212 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
215 #define CONFIG_CONS_INDEX 1
216 #define CONFIG_SYS_NS16550_SERIAL
217 #define CONFIG_SYS_NS16550_REG_SIZE 1
218 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
220 #define CONFIG_SYS_BAUDRATE_TABLE \
221 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
223 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
224 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
229 #define CONFIG_SYS_I2C
230 #define CONFIG_SYS_I2C_FSL
231 #define CONFIG_SYS_FSL_I2C_SPEED 400000
232 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
233 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
234 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
237 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
238 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
239 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
240 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
244 * Memory space is mapped 1-1, but I/O space must start from 0.
246 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
247 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
248 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
249 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
250 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
251 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
252 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
253 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
255 #if defined(CONFIG_PCI)
256 #undef CONFIG_EEPRO100
259 #if !defined(CONFIG_PCI_PNP)
260 #define PCI_ENET0_IOADDR 0xe0000000
261 #define PCI_ENET0_MEMADDR 0xe0000000
262 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
265 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
266 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
268 #endif /* CONFIG_PCI */
270 #if defined(CONFIG_TSEC_ENET)
272 #define CONFIG_MII 1 /* MII PHY management */
273 #define CONFIG_TSEC1 1
274 #define CONFIG_TSEC1_NAME "TSEC0"
275 #define CONFIG_TSEC2 1
276 #define CONFIG_TSEC2_NAME "TSEC1"
277 #define TSEC1_PHY_ADDR 0
278 #define TSEC2_PHY_ADDR 1
279 #define TSEC1_PHYIDX 0
280 #define TSEC2_PHYIDX 0
281 #define TSEC1_FLAGS TSEC_GIGABIT
282 #define TSEC2_FLAGS TSEC_GIGABIT
285 #define CONFIG_MPC85XX_FEC 1
286 #define CONFIG_MPC85XX_FEC_NAME "FEC"
287 #define FEC_PHY_ADDR 3
292 /* Options are: TSEC[0-1], FEC */
293 #define CONFIG_ETHPRIME "TSEC0"
295 #endif /* CONFIG_TSEC_ENET */
300 #ifndef CONFIG_SYS_RAMBOOT
301 #define CONFIG_ENV_IS_IN_FLASH 1
302 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
303 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
304 #define CONFIG_ENV_SIZE 0x2000
306 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
307 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
308 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
309 #define CONFIG_ENV_SIZE 0x2000
312 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
313 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
318 #define CONFIG_BOOTP_BOOTFILESIZE
319 #define CONFIG_BOOTP_BOOTPATH
320 #define CONFIG_BOOTP_GATEWAY
321 #define CONFIG_BOOTP_HOSTNAME
324 * Command line configuration.
326 #define CONFIG_CMD_IRQ
328 #if defined(CONFIG_PCI)
329 #define CONFIG_CMD_PCI
332 #undef CONFIG_WATCHDOG /* watchdog disabled */
335 * Miscellaneous configurable options
337 #define CONFIG_SYS_LONGHELP /* undef to save memory */
338 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
339 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
340 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
342 #if defined(CONFIG_CMD_KGDB)
343 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
345 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
348 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
349 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
350 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
353 * For booting Linux, the board info and command line data
354 * have to be in the first 64 MB of memory, since this is
355 * the maximum mapped by the Linux kernel during initialization.
357 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
358 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
360 #if defined(CONFIG_CMD_KGDB)
361 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
365 * Environment Configuration
368 /* The mac addresses for all ethernet interface */
369 #if defined(CONFIG_TSEC_ENET)
370 #define CONFIG_HAS_ETH0
371 #define CONFIG_HAS_ETH1
372 #define CONFIG_HAS_ETH2
375 #define CONFIG_IPADDR 192.168.1.253
377 #define CONFIG_HOSTNAME unknown
378 #define CONFIG_ROOTPATH "/nfsroot"
379 #define CONFIG_BOOTFILE "your.uImage"
381 #define CONFIG_SERVERIP 192.168.1.1
382 #define CONFIG_GATEWAYIP 192.168.1.1
383 #define CONFIG_NETMASK 255.255.255.0
385 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
387 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
389 #define CONFIG_BAUDRATE 115200
391 #define CONFIG_EXTRA_ENV_SETTINGS \
393 "consoledev=ttyS0\0" \
394 "ramdiskaddr=1000000\0" \
395 "ramdiskfile=your.ramdisk.u-boot\0" \
397 "fdtfile=your.fdt.dtb\0"
399 #define CONFIG_NFSBOOTCOMMAND \
400 "setenv bootargs root=/dev/nfs rw " \
401 "nfsroot=$serverip:$rootpath " \
402 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
403 "console=$consoledev,$baudrate $othbootargs;" \
404 "tftp $loadaddr $bootfile;" \
405 "tftp $fdtaddr $fdtfile;" \
406 "bootm $loadaddr - $fdtaddr"
408 #define CONFIG_RAMBOOTCOMMAND \
409 "setenv bootargs root=/dev/ram rw " \
410 "console=$consoledev,$baudrate $othbootargs;" \
411 "tftp $ramdiskaddr $ramdiskfile;" \
412 "tftp $loadaddr $bootfile;" \
413 "tftp $fdtaddr $fdtfile;" \
414 "bootm $loadaddr $ramdiskaddr $fdtaddr"
416 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
418 #endif /* __CONFIG_H */