2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * mpc8536ds board configuration file
30 /* High Level Configuration Options */
31 #define CONFIG_BOOKE 1 /* BOOKE */
32 #define CONFIG_E500 1 /* BOOKE e500 family */
33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
34 #define CONFIG_MPC8536 1
35 #define CONFIG_MPC8536DS 1
37 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
38 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
39 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */
40 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
41 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
42 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
43 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
44 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
45 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
47 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
49 #define CONFIG_TSEC_ENET /* tsec ethernet support */
50 #define CONFIG_ENV_OVERWRITE
53 * When initializing flash, if we cannot find the manufacturer ID,
54 * assume this is the AMD flash associated with the CDS board.
55 * This allows booting from a promjet.
57 #define CONFIG_ASSUME_AMD_FLASH
60 extern unsigned long get_board_sys_clk(unsigned long dummy);
61 extern unsigned long get_board_ddr_clk(unsigned long dummy);
63 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
64 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
65 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
66 #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
67 from ICS307 instead of switches */
70 * These can be toggled for performance analysis, otherwise use default.
72 #define CONFIG_L2_CACHE /* toggle L2 cache */
73 #define CONFIG_BTB /* toggle branch predition */
75 #define CONFIG_ENABLE_36BIT_PHYS 1
77 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
78 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
79 #define CONFIG_PANIC_HANG /* do not reset board on panic */
82 * Base addresses -- Note these are effective addresses where the
83 * actual resources get mapped (not physical addresses)
85 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
86 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
87 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
88 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
90 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
91 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
92 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
93 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000)
96 #define CONFIG_FSL_DDR2
97 #undef CONFIG_FSL_DDR_INTERACTIVE
98 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
99 #define CONFIG_DDR_SPD
100 #undef CONFIG_DDR_DLL
102 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
103 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
105 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
106 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
108 #define CONFIG_NUM_DDR_CONTROLLERS 1
109 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
110 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
112 /* I2C addresses of SPD EEPROMs */
113 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
114 #define CONFIG_SYS_SPD_BUS_NUM 1
116 /* These are used when DDR doesn't use SPD. */
117 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
118 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
119 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
120 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
121 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
122 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
123 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
124 #define CONFIG_SYS_DDR_MODE_1 0x00480432
125 #define CONFIG_SYS_DDR_MODE_2 0x00000000
126 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
127 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
128 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
129 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
130 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
131 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
132 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
134 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
135 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
136 #define CONFIG_SYS_DDR_SBE 0x00010000
138 /* Make sure required options are set */
139 #ifndef CONFIG_SPD_EEPROM
140 #error ("CONFIG_SPD_EEPROM is required")
143 #undef CONFIG_CLOCKS_IN_MHZ
147 * Memory map -- xxx -this is wrong, needs updating
149 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
150 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
151 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
152 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
154 * Localbus cacheable (TBD)
155 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
157 * Localbus non-cacheable
158 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
159 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
160 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
161 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
162 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
163 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
167 * Local Bus Definitions
169 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
170 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
172 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
173 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
175 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
176 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
178 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
179 #define CONFIG_SYS_FLASH_QUIET_TEST
180 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
182 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
183 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
184 #undef CONFIG_SYS_FLASH_CHECKSUM
185 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
186 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
188 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
190 #define CONFIG_FLASH_CFI_DRIVER
191 #define CONFIG_SYS_FLASH_CFI
192 #define CONFIG_SYS_FLASH_EMPTY_INFO
193 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
195 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
197 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
198 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
199 #define PIXIS_BASE_PHYS PIXIS_BASE
201 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
202 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
204 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
205 #define PIXIS_VER 0x1 /* Board version at offset 1 */
206 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
207 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
208 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
209 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
210 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
211 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
212 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
213 #define PIXIS_VCTL 0x10 /* VELA Control Register */
214 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
215 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
216 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
217 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
218 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
219 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
220 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
221 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
222 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
223 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
224 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
225 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
226 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
227 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
228 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
229 #define PIXIS_LED 0x25 /* LED Register */
231 /* old pixis referenced names */
232 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
233 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
234 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
236 #define CONFIG_SYS_INIT_RAM_LOCK 1
237 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
238 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
240 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
241 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
242 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
244 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
245 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
247 #define CONFIG_SYS_NAND_BASE 0xffa00000
248 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
249 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
250 CONFIG_SYS_NAND_BASE + 0x40000, \
251 CONFIG_SYS_NAND_BASE + 0x80000, \
252 CONFIG_SYS_NAND_BASE + 0xC0000}
253 #define CONFIG_SYS_MAX_NAND_DEVICE 4
254 #define CONFIG_MTD_NAND_VERIFY_WRITE
255 #define CONFIG_CMD_NAND 1
256 #define CONFIG_NAND_FSL_ELBC 1
257 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
259 /* NAND flash config */
260 #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
261 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
262 | BR_PS_8 /* Port Size = 8 bit */ \
263 | BR_MS_FCM /* MSEL = FCM */ \
265 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
266 | OR_FCM_PGS /* Large Page*/ \
274 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
275 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
277 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
278 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
279 | BR_PS_8 /* Port Size = 8 bit */ \
280 | BR_MS_FCM /* MSEL = FCM */ \
282 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
283 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
284 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
285 | BR_PS_8 /* Port Size = 8 bit */ \
286 | BR_MS_FCM /* MSEL = FCM */ \
288 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
290 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
291 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
292 | BR_PS_8 /* Port Size = 8 bit */ \
293 | BR_MS_FCM /* MSEL = FCM */ \
295 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
297 /* Serial Port - controlled on board with jumper J8
301 #define CONFIG_CONS_INDEX 1
302 #undef CONFIG_SERIAL_SOFTWARE_FIFO
303 #define CONFIG_SYS_NS16550
304 #define CONFIG_SYS_NS16550_SERIAL
305 #define CONFIG_SYS_NS16550_REG_SIZE 1
306 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
308 #define CONFIG_SYS_BAUDRATE_TABLE \
309 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
311 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
312 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
314 /* Use the HUSH parser */
315 #define CONFIG_SYS_HUSH_PARSER
316 #ifdef CONFIG_SYS_HUSH_PARSER
317 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
321 * Pass open firmware flat tree
323 #define CONFIG_OF_LIBFDT 1
324 #define CONFIG_OF_BOARD_SETUP 1
325 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
327 #define CONFIG_SYS_64BIT_STRTOUL 1
328 #define CONFIG_SYS_64BIT_VSPRINTF 1
334 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
335 #define CONFIG_HARD_I2C /* I2C with hardware support */
336 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
337 #define CONFIG_I2C_MULTI_BUS
338 #define CONFIG_I2C_CMD_TREE
339 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
340 #define CONFIG_SYS_I2C_SLAVE 0x7F
341 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */
342 #define CONFIG_SYS_I2C_OFFSET 0x3000
343 #define CONFIG_SYS_I2C2_OFFSET 0x3100
348 #define CONFIG_ID_EEPROM
349 #ifdef CONFIG_ID_EEPROM
350 #define CONFIG_SYS_I2C_EEPROM_NXID
352 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
353 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
354 #define CONFIG_SYS_EEPROM_BUS_NUM 1
358 * Memory space is mapped 1-1, but I/O space must start from 0.
361 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
362 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
363 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
364 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
365 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
366 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
367 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
368 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
370 /* controller 1, Slot 1, tgtid 1, Base address a000 */
371 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
372 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
373 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
374 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
375 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
376 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
377 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
378 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
380 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
381 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
382 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
383 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
384 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
385 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
386 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
387 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
388 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
390 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
391 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
392 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
393 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
394 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
395 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
396 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
397 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
398 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
400 #if defined(CONFIG_PCI)
402 #define CONFIG_NET_MULTI
403 #define CONFIG_PCI_PNP /* do pci plug-and-play */
405 /*PCIE video card used*/
406 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
408 /*PCI video card used*/
409 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
414 #if defined(CONFIG_VIDEO)
415 #define CONFIG_BIOSEMU
416 #define CONFIG_CFB_CONSOLE
417 #define CONFIG_VIDEO_SW_CURSOR
418 #define CONFIG_VGA_AS_SINGLE_DEVICE
419 #define CONFIG_ATI_RADEON_FB
420 #define CONFIG_VIDEO_LOGO
421 /*#define CONFIG_CONSOLE_CURSOR*/
422 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
425 #undef CONFIG_EEPRO100
427 #undef CONFIG_RTL8139
429 #ifdef CONFIG_RTL8139
430 /* This macro is used by RTL8139 but not defined in PPC architecture */
431 #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
432 #define _IO_BASE 0x00000000
435 #ifndef CONFIG_PCI_PNP
436 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
437 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
438 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
441 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
443 #endif /* CONFIG_PCI */
446 #define CONFIG_LIBATA
447 #define CONFIG_FSL_SATA
449 #define CONFIG_SYS_SATA_MAX_DEVICE 2
451 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
452 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
454 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
455 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
457 #ifdef CONFIG_FSL_SATA
459 #define CONFIG_CMD_SATA
460 #define CONFIG_DOS_PARTITION
461 #define CONFIG_CMD_EXT2
464 #if defined(CONFIG_TSEC_ENET)
466 #ifndef CONFIG_NET_MULTI
467 #define CONFIG_NET_MULTI 1
470 #define CONFIG_MII 1 /* MII PHY management */
471 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
472 #define CONFIG_TSEC1 1
473 #define CONFIG_TSEC1_NAME "eTSEC1"
474 #define CONFIG_TSEC3 1
475 #define CONFIG_TSEC3_NAME "eTSEC3"
477 #define CONFIG_FSL_SGMII_RISER 1
478 #define SGMII_RISER_PHY_OFFSET 0x1c
480 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
481 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
483 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
484 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
486 #define TSEC1_PHYIDX 0
487 #define TSEC3_PHYIDX 0
489 #define CONFIG_ETHPRIME "eTSEC1"
491 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
493 #endif /* CONFIG_TSEC_ENET */
498 #define CONFIG_ENV_IS_IN_FLASH 1
499 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
500 #define CONFIG_ENV_ADDR 0xfff80000
502 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
504 #define CONFIG_ENV_SIZE 0x2000
505 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
507 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
508 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
511 * Command line configuration.
513 #include <config_cmd_default.h>
515 #define CONFIG_CMD_IRQ
516 #define CONFIG_CMD_PING
517 #define CONFIG_CMD_I2C
518 #define CONFIG_CMD_MII
519 #define CONFIG_CMD_ELF
520 #define CONFIG_CMD_IRQ
521 #define CONFIG_CMD_SETEXPR
523 #if defined(CONFIG_PCI)
524 #define CONFIG_CMD_PCI
525 #define CONFIG_CMD_BEDBUG
526 #define CONFIG_CMD_NET
529 #undef CONFIG_WATCHDOG /* watchdog disabled */
532 * Miscellaneous configurable options
534 #define CONFIG_SYS_LONGHELP /* undef to save memory */
535 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
536 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
537 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
538 #if defined(CONFIG_CMD_KGDB)
539 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
541 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
543 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
544 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
545 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
546 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
549 * For booting Linux, the board info and command line data
550 * have to be in the first 8 MB of memory, since this is
551 * the maximum mapped by the Linux kernel during initialization.
553 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
556 * Internal Definitions
560 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
561 #define BOOTFLAG_WARM 0x02 /* Software reboot */
563 #if defined(CONFIG_CMD_KGDB)
564 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
565 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
569 * Environment Configuration
572 /* The mac addresses for all ethernet interface */
573 #if defined(CONFIG_TSEC_ENET)
574 #define CONFIG_HAS_ETH0
575 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
576 #define CONFIG_HAS_ETH1
577 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
578 #define CONFIG_HAS_ETH2
579 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
580 #define CONFIG_HAS_ETH3
581 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
584 #define CONFIG_IPADDR 192.168.1.254
586 #define CONFIG_HOSTNAME unknown
587 #define CONFIG_ROOTPATH /opt/nfsroot
588 #define CONFIG_BOOTFILE uImage
589 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
591 #define CONFIG_SERVERIP 192.168.1.1
592 #define CONFIG_GATEWAYIP 192.168.1.1
593 #define CONFIG_NETMASK 255.255.255.0
595 /* default location for tftp and bootm */
596 #define CONFIG_LOADADDR 1000000
598 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
599 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
601 #define CONFIG_BAUDRATE 115200
603 #define CONFIG_EXTRA_ENV_SETTINGS \
605 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
606 "tftpflash=tftpboot $loadaddr $uboot; " \
607 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
608 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
609 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
610 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
611 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
612 "consoledev=ttyS0\0" \
613 "ramdiskaddr=2000000\0" \
614 "ramdiskfile=8536ds/ramdisk.uboot\0" \
616 "fdtfile=8536ds/mpc8536ds.dtb\0" \
619 #define CONFIG_HDBOOT \
620 "setenv bootargs root=/dev/$bdev rw " \
621 "console=$consoledev,$baudrate $othbootargs;" \
622 "tftp $loadaddr $bootfile;" \
623 "tftp $fdtaddr $fdtfile;" \
624 "bootm $loadaddr - $fdtaddr"
626 #define CONFIG_NFSBOOTCOMMAND \
627 "setenv bootargs root=/dev/nfs rw " \
628 "nfsroot=$serverip:$rootpath " \
629 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
630 "console=$consoledev,$baudrate $othbootargs;" \
631 "tftp $loadaddr $bootfile;" \
632 "tftp $fdtaddr $fdtfile;" \
633 "bootm $loadaddr - $fdtaddr"
635 #define CONFIG_RAMBOOTCOMMAND \
636 "setenv bootargs root=/dev/ram rw " \
637 "console=$consoledev,$baudrate $othbootargs;" \
638 "tftp $ramdiskaddr $ramdiskfile;" \
639 "tftp $loadaddr $bootfile;" \
640 "tftp $fdtaddr $fdtfile;" \
641 "bootm $loadaddr $ramdiskaddr $fdtaddr"
643 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
645 #endif /* __CONFIG_H */