1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
7 * mpc8536ds board configuration file
13 #include <linux/stringify.h>
15 #include "../board/freescale/common/ics307_clk.h"
18 #define CONFIG_RAMBOOT_SDCARD 1
19 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
22 #ifdef CONFIG_SPIFLASH
23 #define CONFIG_RAMBOOT_SPIFLASH 1
24 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
27 #ifndef CONFIG_RESET_VECTOR_ADDRESS
28 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
31 #ifndef CONFIG_SYS_MONITOR_BASE
32 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
35 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */
36 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
37 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
38 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
39 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
40 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
41 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
44 #define CONFIG_ENV_OVERWRITE
46 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
47 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
48 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
51 * These can be toggled for performance analysis, otherwise use default.
53 #define CONFIG_L2_CACHE /* toggle L2 cache */
54 #define CONFIG_BTB /* toggle branch predition */
56 #define CONFIG_ENABLE_36BIT_PHYS 1
58 #ifdef CONFIG_PHYS_64BIT
59 #define CONFIG_ADDR_MAP 1
60 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
64 * Config the L2 Cache as L2 SRAM
66 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
67 #ifdef CONFIG_PHYS_64BIT
68 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
70 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
72 #define CONFIG_SYS_L2_SIZE (512 << 10)
73 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
75 #define CONFIG_SYS_CCSRBAR 0xffe00000
76 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
78 #if defined(CONFIG_NAND_SPL)
79 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
83 #define CONFIG_VERY_BIG_RAM
84 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
85 #define CONFIG_DDR_SPD
87 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
88 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
90 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
91 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
93 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
94 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
96 /* I2C addresses of SPD EEPROMs */
97 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
98 #define CONFIG_SYS_SPD_BUS_NUM 1
100 /* These are used when DDR doesn't use SPD. */
101 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
102 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
103 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
104 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
105 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
106 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
107 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
108 #define CONFIG_SYS_DDR_MODE_1 0x00480432
109 #define CONFIG_SYS_DDR_MODE_2 0x00000000
110 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
111 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
112 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
113 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
114 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
115 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
116 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
118 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
119 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
120 #define CONFIG_SYS_DDR_SBE 0x00010000
122 /* Make sure required options are set */
123 #ifndef CONFIG_SPD_EEPROM
124 #error ("CONFIG_SPD_EEPROM is required")
127 #undef CONFIG_CLOCKS_IN_MHZ
130 * Memory map -- xxx -this is wrong, needs updating
132 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
133 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
134 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
135 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
137 * Localbus cacheable (TBD)
138 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
140 * Localbus non-cacheable
141 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
142 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
143 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
144 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
145 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
146 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
150 * Local Bus Definitions
152 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
153 #ifdef CONFIG_PHYS_64BIT
154 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
156 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
159 #define CONFIG_FLASH_BR_PRELIM \
160 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
161 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
163 #define CONFIG_SYS_BR1_PRELIM \
164 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
166 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
168 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
169 CONFIG_SYS_FLASH_BASE_PHYS }
170 #define CONFIG_SYS_FLASH_QUIET_TEST
171 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
173 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
174 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
175 #undef CONFIG_SYS_FLASH_CHECKSUM
176 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
177 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
179 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
180 #define CONFIG_SYS_RAMBOOT
182 #undef CONFIG_SYS_RAMBOOT
185 #define CONFIG_SYS_FLASH_EMPTY_INFO
186 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
188 #define CONFIG_HWCONFIG /* enable hwconfig */
189 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
190 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
191 #ifdef CONFIG_PHYS_64BIT
192 #define PIXIS_BASE_PHYS 0xfffdf0000ull
194 #define PIXIS_BASE_PHYS PIXIS_BASE
197 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
198 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
200 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
201 #define PIXIS_VER 0x1 /* Board version at offset 1 */
202 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
203 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
204 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
205 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
206 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
207 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
208 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
209 #define PIXIS_VCTL 0x10 /* VELA Control Register */
210 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
211 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
212 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
213 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
214 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
215 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
216 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
217 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
218 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
219 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
220 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
221 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
222 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
223 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
224 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
225 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
226 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
227 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
228 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
229 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
230 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
231 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
232 #define PIXIS_LED 0x25 /* LED Register */
234 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
236 /* old pixis referenced names */
237 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
238 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
239 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
241 #define CONFIG_SYS_INIT_RAM_LOCK 1
242 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
243 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
245 #define CONFIG_SYS_GBL_DATA_OFFSET \
246 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
247 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
249 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
250 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
252 #ifndef CONFIG_NAND_SPL
253 #define CONFIG_SYS_NAND_BASE 0xffa00000
254 #ifdef CONFIG_PHYS_64BIT
255 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
257 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
260 #define CONFIG_SYS_NAND_BASE 0xfff00000
261 #ifdef CONFIG_PHYS_64BIT
262 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
264 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
267 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
268 CONFIG_SYS_NAND_BASE + 0x40000, \
269 CONFIG_SYS_NAND_BASE + 0x80000, \
270 CONFIG_SYS_NAND_BASE + 0xC0000}
271 #define CONFIG_SYS_MAX_NAND_DEVICE 4
272 #define CONFIG_NAND_FSL_ELBC 1
273 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
275 /* NAND boot: 4K NAND loader config */
276 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
277 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
278 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
279 #define CONFIG_SYS_NAND_U_BOOT_START \
280 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
281 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
282 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
283 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
285 /* NAND flash config */
286 #define CONFIG_SYS_NAND_BR_PRELIM \
287 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
288 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
289 | BR_PS_8 /* Port Size = 8 bit */ \
290 | BR_MS_FCM /* MSEL = FCM */ \
292 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
293 | OR_FCM_PGS /* Large Page*/ \
301 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
302 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
303 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
304 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
306 #define CONFIG_SYS_BR4_PRELIM \
307 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
308 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
309 | BR_PS_8 /* Port Size = 8 bit */ \
310 | BR_MS_FCM /* MSEL = FCM */ \
312 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
313 #define CONFIG_SYS_BR5_PRELIM \
314 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
315 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
316 | BR_PS_8 /* Port Size = 8 bit */ \
317 | BR_MS_FCM /* MSEL = FCM */ \
319 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
321 #define CONFIG_SYS_BR6_PRELIM \
322 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
323 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
324 | BR_PS_8 /* Port Size = 8 bit */ \
325 | BR_MS_FCM /* MSEL = FCM */ \
327 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
329 /* Serial Port - controlled on board with jumper J8
333 #define CONFIG_SYS_NS16550_SERIAL
334 #define CONFIG_SYS_NS16550_REG_SIZE 1
335 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
336 #ifdef CONFIG_NAND_SPL
337 #define CONFIG_NS16550_MIN_FUNCTIONS
340 #define CONFIG_SYS_BAUDRATE_TABLE \
341 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
343 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
344 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
349 #define CONFIG_SYS_I2C
350 #define CONFIG_SYS_I2C_FSL
351 #define CONFIG_SYS_FSL_I2C_SPEED 400000
352 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
353 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
354 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
355 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
356 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
357 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
362 #define CONFIG_ID_EEPROM
363 #ifdef CONFIG_ID_EEPROM
364 #define CONFIG_SYS_I2C_EEPROM_NXID
366 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
367 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
368 #define CONFIG_SYS_EEPROM_BUS_NUM 1
372 * Memory space is mapped 1-1, but I/O space must start from 0.
375 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
376 #ifdef CONFIG_PHYS_64BIT
377 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
378 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
380 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
381 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
383 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
384 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
385 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
386 #ifdef CONFIG_PHYS_64BIT
387 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
389 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
391 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
393 /* controller 1, Slot 1, tgtid 1, Base address a000 */
394 #define CONFIG_SYS_PCIE1_NAME "Slot 1"
395 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
396 #ifdef CONFIG_PHYS_64BIT
397 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
398 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
400 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
401 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
403 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
404 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
405 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
406 #ifdef CONFIG_PHYS_64BIT
407 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
409 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
411 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
413 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
414 #define CONFIG_SYS_PCIE2_NAME "Slot 2"
415 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
416 #ifdef CONFIG_PHYS_64BIT
417 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
418 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
420 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
421 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
423 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
424 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
425 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
426 #ifdef CONFIG_PHYS_64BIT
427 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
429 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
431 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
433 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
434 #define CONFIG_SYS_PCIE3_NAME "Slot 3"
435 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
436 #ifdef CONFIG_PHYS_64BIT
437 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
438 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
440 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
441 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
443 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
444 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
445 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
446 #ifdef CONFIG_PHYS_64BIT
447 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
449 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
451 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
453 #if defined(CONFIG_PCI)
454 /*PCIE video card used*/
455 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
457 /*PCI video card used*/
458 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
462 #if defined(CONFIG_VIDEO)
463 #define CONFIG_BIOSEMU
464 #define CONFIG_ATI_RADEON_FB
465 #define CONFIG_VIDEO_LOGO
466 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
469 #undef CONFIG_EEPRO100
472 #ifndef CONFIG_PCI_PNP
473 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
474 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
475 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
478 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
480 #endif /* CONFIG_PCI */
483 #define CONFIG_SYS_SATA_MAX_DEVICE 2
485 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
486 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
488 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
489 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
491 #ifdef CONFIG_FSL_SATA
495 #if defined(CONFIG_TSEC_ENET)
497 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
498 #define CONFIG_TSEC1 1
499 #define CONFIG_TSEC1_NAME "eTSEC1"
500 #define CONFIG_TSEC3 1
501 #define CONFIG_TSEC3_NAME "eTSEC3"
503 #define CONFIG_FSL_SGMII_RISER 1
504 #define SGMII_RISER_PHY_OFFSET 0x1c
506 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
507 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
509 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
510 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
512 #define TSEC1_PHYIDX 0
513 #define TSEC3_PHYIDX 0
515 #define CONFIG_ETHPRIME "eTSEC1"
517 #endif /* CONFIG_TSEC_ENET */
523 #if defined(CONFIG_SYS_RAMBOOT)
524 #if defined(CONFIG_RAMBOOT_SPIFLASH)
525 #elif defined(CONFIG_RAMBOOT_SDCARD)
526 #define CONFIG_FSL_FIXED_MMC_LOCATION
527 #define CONFIG_SYS_MMC_ENV_DEV 0
531 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
532 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
534 #undef CONFIG_WATCHDOG /* watchdog disabled */
537 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
543 #define CONFIG_HAS_FSL_MPH_USB
544 #ifdef CONFIG_HAS_FSL_MPH_USB
545 #ifdef CONFIG_USB_EHCI_HCD
546 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
547 #define CONFIG_USB_EHCI_FSL
552 * Miscellaneous configurable options
554 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
557 * For booting Linux, the board info and command line data
558 * have to be in the first 64 MB of memory, since this is
559 * the maximum mapped by the Linux kernel during initialization.
561 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
562 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
564 #if defined(CONFIG_CMD_KGDB)
565 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
569 * Environment Configuration
572 /* The mac addresses for all ethernet interface */
573 #if defined(CONFIG_TSEC_ENET)
574 #define CONFIG_HAS_ETH0
575 #define CONFIG_HAS_ETH1
576 #define CONFIG_HAS_ETH2
577 #define CONFIG_HAS_ETH3
580 #define CONFIG_IPADDR 192.168.1.254
582 #define CONFIG_HOSTNAME "unknown"
583 #define CONFIG_ROOTPATH "/opt/nfsroot"
584 #define CONFIG_BOOTFILE "uImage"
585 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
587 #define CONFIG_SERVERIP 192.168.1.1
588 #define CONFIG_GATEWAYIP 192.168.1.1
589 #define CONFIG_NETMASK 255.255.255.0
591 /* default location for tftp and bootm */
592 #define CONFIG_LOADADDR 1000000
594 #define CONFIG_EXTRA_ENV_SETTINGS \
596 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
597 "tftpflash=tftpboot $loadaddr $uboot; " \
598 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
600 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
602 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
604 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
606 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
608 "consoledev=ttyS0\0" \
609 "ramdiskaddr=2000000\0" \
610 "ramdiskfile=8536ds/ramdisk.uboot\0" \
611 "fdtaddr=1e00000\0" \
612 "fdtfile=8536ds/mpc8536ds.dtb\0" \
614 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
616 #define CONFIG_HDBOOT \
617 "setenv bootargs root=/dev/$bdev rw " \
618 "console=$consoledev,$baudrate $othbootargs;" \
619 "tftp $loadaddr $bootfile;" \
620 "tftp $fdtaddr $fdtfile;" \
621 "bootm $loadaddr - $fdtaddr"
623 #define CONFIG_NFSBOOTCOMMAND \
624 "setenv bootargs root=/dev/nfs rw " \
625 "nfsroot=$serverip:$rootpath " \
626 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
627 "console=$consoledev,$baudrate $othbootargs;" \
628 "tftp $loadaddr $bootfile;" \
629 "tftp $fdtaddr $fdtfile;" \
630 "bootm $loadaddr - $fdtaddr"
632 #define CONFIG_RAMBOOTCOMMAND \
633 "setenv bootargs root=/dev/ram rw " \
634 "console=$consoledev,$baudrate $othbootargs;" \
635 "tftp $ramdiskaddr $ramdiskfile;" \
636 "tftp $loadaddr $bootfile;" \
637 "tftp $fdtaddr $fdtfile;" \
638 "bootm $loadaddr $ramdiskaddr $fdtaddr"
640 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
642 #endif /* __CONFIG_H */